Re: [PATCH v2 13/14] net: mediatek: add support for MediaTek MT7621 SoC

On Fri, Nov 19, 2021 at 3:37 AM Weijie Gao weijie.gao@mediatek.com wrote:

This patch adds GMAC support for MediaTek MT7621 SoC. MT7621 has the same GMAC/Switch configuration as MT7623.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com

v2 changes: none

drivers/net/mtk_eth.c | 27 +++++++++++++++++++++------ drivers/net/mtk_eth.h | 8 ++++++++ 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 26f02847a2..3b42c99c2a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -145,7 +145,8 @@ enum mtk_switch { enum mtk_soc { SOC_MT7623, SOC_MT7629,

•   SOC_MT7622
  

•   SOC_MT7622,
  

•   SOC_MT7621
  

};

struct mtk_eth_priv { @@ -669,12 +670,18 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) static int mt7530_setup(struct mtk_eth_priv *priv) { u16 phy_addr, phy_val;

•   u32 val;
  

•   u32 val, txdrv;
    int i;
  
  

•   /* Select 250MHz clk for RGMII mode */
  

•   mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  

•                  ETHSYS_TRGMII_CLK_SEL362_5, 0);
  

•   if (priv->soc != SOC_MT7621) {
  

•           /* Select 250MHz clk for RGMII mode */
  

•           mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  

•                          ETHSYS_TRGMII_CLK_SEL362_5, 0);
  

•           txdrv = 8;
  

•   } else {
  

•           txdrv = 4;
  

•   }
  
    /* Modify HWTRAP first to allow direct access to internal PHYs */
    mt753x_reg_read(priv, HWTRAP_REG, &val);
  

@@ -732,7 +739,8 @@ static int mt7530_setup(struct mtk_eth_priv *priv) /* Lower Tx Driving for TRGMII path */ for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),

•                            (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
  

•                            (txdrv << TD_DM_DRVP_S) |
  

•                            (txdrv << TD_DM_DRVN_S));
  
    for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
            mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
  

@@ -1437,6 +1445,12 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return -ENODEV; }

•   if (priv->soc == SOC_MT7621) {
  

•           /* ioremap is needed for MIPS platform */
  

For MIPS ? you need to io map for every platform, some platform just works without it.

•           priv->ethsys_base =
  

•                   ioremap_nocache((phys_addr_t)priv->ethsys_base, 0x100);
  

•   }
  

•   /* Reset controllers */
    ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
    if (ret) {
  

@@ -1542,6 +1556,7 @@ static const struct udevice_id mtk_eth_ids[] = { { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },

•   { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
    {}
  

};

diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 057ecfaabf..4a8c66c671 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -412,4 +412,12 @@ #define PHY_POWER_SAVING_M 0x300 #define PHY_POWER_SAVING_TX 0x0

+#ifndef CONFIG_SYS_NONCACHED_MEMORY +/*

• • noncached_alloc is provided only for ARM. Add a prototype here for other
• • platforms to suppress compilation warning.
• */

+phys_addr_t noncached_alloc(size_t size, size_t align);

That's not the place for that. I assume that it fails on MIPS, please create a patch for MIPS arch.

+#endif

#endif /* _MTK_ETH_H_ */

2.17.1