7 May
2018
7 May
'18
11:25 p.m.
On Mon, May 7, 2018 at 10:11 PM Mans Rullgard mans@mansr.com wrote:
The lowlevel_init function uses r4 and r6 without preserving their values as required by the AAPCS. Use r0 and r2 instead as these are call-clobbered.
Signed-off-by: Mans Rullgard mans@mansr.com
arch/arm/mach-orion5x/lowlevel_init.S | 168 +++++++++++++------------- 1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-orion5x/lowlevel_init.S
b/arch/arm/mach-orion5x/lowlevel_init.S
index 3f38f36ff294..a4e113601013 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -72,67 +72,67 @@ lowlevel_init:
#ifdef CONFIG_SPL_BUILD
/* Use 'r4 as the base for internal register accesses */ldr r4, =ORION5X_REGS_PHY_BASE
/* Use 'r2 as the base for internal register accesses */ldr r2, =ORION5X_REGS_PHY_BASE
/* move internal registers from the default 0xD0000000 * to their intended location, defined by SoC */ ldr r3, =0xD0000000 add r3, r3, #0x20000
str r4, [r3, #0x80]
str r2, [r3, #0x80]
/* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
add r3, r2, #0x01000
/*DDR SDRAM Initialization Control */
ldr r6, =0x00000001str r6, [r3, #0x480]
ldr r0, =0x00000001str r0, [r3, #0x480]
/* Use R3 as the base for PCI registers */
add r3, r4, #0x31000
add r3, r2, #0x31000
/* Disable arbiter */
ldr r6, =0x00000030str r6, [r3, #0xd00]
ldr r0, =0x00000030str r0, [r3, #0xd00]
/* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
add r3, r2, #0x01000
/* set all dram windows to 0 */
mov r6, #0str r6, [r3, #0x504]str r6, [r3, #0x50C]str r6, [r3, #0x514]str r6, [r3, #0x51C]
mov r0, #0str r0, [r3, #0x504]str r0, [r3, #0x50C]str r0, [r3, #0x514]str r0, [r3, #0x51C]
/* 1) Configure SDRAM */
ldr r6, =SDRAM_CONFIGstr r6, [r3, #0x400]
ldr r0, =SDRAM_CONFIGstr r0, [r3, #0x400]
/* 2) Set SDRAM Control reg */
ldr r6, =SDRAM_CONTROLstr r6, [r3, #0x404]
ldr r0, =SDRAM_CONTROLstr r0, [r3, #0x404]
/* 3) Write SDRAM address control register */
ldr r6, =SDRAM_ADDR_CTRLstr r6, [r3, #0x410]
ldr r0, =SDRAM_ADDR_CTRLstr r0, [r3, #0x410]
/* 4) Write SDRAM bank 0 size register */
ldr r6, =SDRAM_BANK0_SIZEstr r6, [r3, #0x504]
ldr r0, =SDRAM_BANK0_SIZEstr r0, [r3, #0x504] /* keep other banks disabled */
/* 5) Write SDRAM open pages control register */
ldr r6, =SDRAM_OPEN_PAGE_ENstr r6, [r3, #0x414]
ldr r0, =SDRAM_OPEN_PAGE_ENstr r0, [r3, #0x414]
/* 6) Write SDRAM timing Low register */
ldr r6, =SDRAM_TIME_CTRL_LOWstr r6, [r3, #0x408]
ldr r0, =SDRAM_TIME_CTRL_LOWstr r0, [r3, #0x408]
/* 7) Write SDRAM timing High register */
ldr r6, =SDRAM_TIME_CTRL_HIstr r6, [r3, #0x40C]
ldr r0, =SDRAM_TIME_CTRL_HIstr r0, [r3, #0x40C]
/* 8) Write SDRAM mode register */ /* The CPU must not attempt to change the SDRAM Mode register
setting */
@@ -143,73 +143,73 @@ lowlevel_init: /* and then sets SDRAM Mode register to its new value.
*/
/* 8.1 write 'nop' to SDRAM operation */
ldr r6, =SDRAM_OP_NOPstr r6, [r3, #0x418]
ldr r0, =SDRAM_OP_NOPstr r0, [r3, #0x418]
/* 8.2 poll SDRAM operation until back in 'normal' mode. */1:
ldr r6, [r3, #0x418]cmp r6, #0
ldr r0, [r3, #0x418]cmp r0, #0 bne 1b
/* 8.3 Now its safe to write new value to SDRAM Mode register
*/
ldr r6, =SDRAM_MODEstr r6, [r3, #0x41C]
ldr r0, =SDRAM_MODEstr r0, [r3, #0x41C]
/* 8.4 Set new mode */
ldr r6, =SDRAM_OP_SETMODEstr r6, [r3, #0x418]
ldr r0, =SDRAM_OP_SETMODEstr r0, [r3, #0x418]
/* 8.5 poll SDRAM operation until back in 'normal' mode. */2:
ldr r6, [r3, #0x418]cmp r6, #0
ldr r0, [r3, #0x418]cmp r0, #0 bne 2b
/* DDR SDRAM Address/Control Pads Calibration */
ldr r6, [r3, #0x4C0]
ldr r0, [r3, #0x4C0]
/* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]
orr r0, r0, #SDRAM_PAD_CTRL_WR_ENstr r0, [r3, #0x4C0]
bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
bic r0, r0, #SDRAM_PAD_CTRL_WR_ENbic r0, r0, #SDRAM_PAD_CTRL_TUNE_ENbic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASKbic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r6
mov r1, r0 mov r1, r1, LSL #9 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1str r6, [r3, #0x4C0]
orr r0, r0, r1str r0, [r3, #0x4C0]
/* DDR SDRAM Data Pads Calibration */
ldr r6, [r3, #0x4C4]
ldr r0, [r3, #0x4C4]
/* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]
orr r0, r0, #SDRAM_PAD_CTRL_WR_ENstr r0, [r3, #0x4C4]
bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
bic r0, r0, #SDRAM_PAD_CTRL_WR_ENbic r0, r0, #SDRAM_PAD_CTRL_TUNE_ENbic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASKbic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
/* Get the final N locked value of driving strength [22:17] */
mov r1, r6
mov r1, r0 mov r1, r1, LSL #9 mov r1, r1, LSR #26 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1
orr r0, r0, r1
str r6, [r3, #0x4C4]
str r0, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-3) Drive Strength Value */ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */@@ -217,37 +217,37 @@ lowlevel_init: ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register
*/
ldr r6, [r3, #0x4C0]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]
ldr r0, [r3, #0x4C0]orr r0, r0, #SDRAM_PAD_CTRL_WR_ENstr r0, [r3, #0x4C0]
/* Correct strength and disable writes again */
bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r6, r6, r1str r6, [r3, #0x4C0]
bic r0, r0, #SDRAM_PAD_CTRL_WR_ENbic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r0, r0, r1str r0, [r3, #0x4C0]
/* Enable writes to DDR SDRAM Data Pads Calibration register */
ldr r6, [r3, #0x4C4]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]
ldr r0, [r3, #0x4C4]orr r0, r0, #SDRAM_PAD_CTRL_WR_ENstr r0, [r3, #0x4C4]
/* Correct strength and disable writes again */
bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r6, r6, #SDRAM_PAD_CTRL_WR_ENorr r6, r6, r1str r6, [r3, #0x4C4]
bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r0, r0, #SDRAM_PAD_CTRL_WR_ENorr r0, r0, r1str r0, [r3, #0x4C4]
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
/* Get the "sample on reset" register for the DDR frequancy */ ldr r3, =0x10000
ldr r6, [r3, #0x010]
ldr r0, [r3, #0x010] ldr r1, =MSAR_ARMDDRCLCK_MASK
and r1, r6, r1
and r1, r0, r1
ldr r6, =FTDLL_DDR1_166MHZ
ldr r0, =FTDLL_DDR1_166MHZ cmp r1, #MSAR_ARMDDRCLCK_333_167 beq 3f cmp r1, #MSAR_ARMDDRCLCK_500_167@@ -255,7 +255,7 @@ lowlevel_init: cmp r1, #MSAR_ARMDDRCLCK_667_167 beq 3f
ldr r6, =FTDLL_DDR1_200MHZ
ldr r0, =FTDLL_DDR1_200MHZ cmp r1, #MSAR_ARMDDRCLCK_400_200_1 beq 3f cmp r1, #MSAR_ARMDDRCLCK_400_200@@ -265,21 +265,21 @@ lowlevel_init: cmp r1, #MSAR_ARMDDRCLCK_800_200 beq 3f
ldr r6, =0
ldr r0, =0
3: /* Use R3 as the base for DRAM registers */
add r3, r4, #0x01000
add r3, r2, #0x01000
ldr r2, [r3, #0x484]
orr r2, r2, r6
orr r2, r2, r0 str r2, [r3, #0x484]
/* enable for 2 GB DDR; detection should find out real amount */
sub r6, r6, r6str r6, [r3, #0x500]ldr r6, =0x7fff0001str r6, [r3, #0x504]
sub r0, r0, r0str r0, [r3, #0x500]ldr r0, =0x7fff0001str r0, [r3, #0x504]
#endif /* CONFIG_SPL_BUILD */
Looks good to me
Reviewed-by: Chris Packham judge.packham@gmail.com