ftahbc020s.h provides the basic definitions to help a SoC which use this AHB Controller could do scalable software settings in both C codes and asm codes.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- include/faraday/ftahbc020s.h | 72 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 include/faraday/ftahbc020s.h
diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h new file mode 100644 index 0000000..5a18e86 --- /dev/null +++ b/include/faraday/ftahbc020s.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions + */ +#ifndef __FTAHBC020S_H +#define __FTAHBC202S_H + +/* + * Registers Offsets + */ +#define FTAHBC020S_SLAVE_BSR_0 0x00 /* Slave n Base/Size Reg */ +#define FTAHBC020S_SLAVE_BSR_1 0x04 +#define FTAHBC020S_SLAVE_BSR_2 0x08 +#define FTAHBC020S_SLAVE_BSR_3 0x0C +#define FTAHBC020S_SLAVE_BSR_4 0x10 +#define FTAHBC020S_SLAVE_BSR_5 0x14 +#define FTAHBC020S_SLAVE_BSR_6 0x18 +#define FTAHBC020S_SLAVE_BSR_7 0x1C +#define FTAHBC020S_SLAVE_BSR_8 0x20 +#define FTAHBC020S_SLAVE_BSR_9 0x24 +#define FTAHBC020S_SLAVE_BSR_10 0x28 + +#define FTAHBC020S_PCR 0x80 /* Priority Ctrl Reg */ +#define FTAHBC020S_TCRG 0x84 /* Transfer Ctrl Reg */ +#define FTAHBC020S_CR 0x88 /* Ctrl Reg */ + +/* FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register */ +#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xFFF) << 20) +#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xF) << 16) + +/* FTAHBC020S_PCR - Priority Control Register */ +#define FTAHBC020S_PCR_PLEVEL_15 (1 << 15) +#define FTAHBC020S_PCR_PLEVEL_14 (1 << 14) +#define FTAHBC020S_PCR_PLEVEL_13 (1 << 13) +#define FTAHBC020S_PCR_PLEVEL_12 (1 << 12) +#define FTAHBC020S_PCR_PLEVEL_11 (1 << 11) +#define FTAHBC020S_PCR_PLEVEL_10 (1 << 10) +#define FTAHBC020S_PCR_PLEVEL_09 (1 << 9) +#define FTAHBC020S_PCR_PLEVEL_08 (1 << 8) +#define FTAHBC020S_PCR_PLEVEL_07 (1 << 7) +#define FTAHBC020S_PCR_PLEVEL_06 (1 << 6) +#define FTAHBC020S_PCR_PLEVEL_05 (1 << 5) +#define FTAHBC020S_PCR_PLEVEL_04 (1 << 4) +#define FTAHBC020S_PCR_PLEVEL_03 (1 << 3) +#define FTAHBC020S_PCR_PLEVEL_02 (1 << 2) +#define FTAHBC020S_PCR_PLEVEL_01 (1 << 1) + +/* FTAHBC020S_CR - Interrupt Control Register */ +#define FTAHBC020S_CR_INTSTS (1 << 24) +#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) +#define FTAHBC020S_CR_INTSMASK (1 << 16) +#define FTAHBC020S_CR_REMAP (1 << 0) + +#endif /* __FTAHBC020S_H */