Hi Simon,
On Thu, Aug 29, 2013 at 8:31 PM, Simon Glass sjg@chromium.org wrote:
On Thu, Aug 29, 2013 at 5:04 AM, Rajeshwari Birje rajeshwari.birje@gmail.com wrote:
CCing the MMC Maintainer.
On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde rajeshwari.s@samsung.com wrote:
This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde rajeshwari.s@samsung.com
arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- include/dwmmc.h | 2 +- 4 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index b9eca76..f1c8d8a 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -14,6 +14,10 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7
#ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a82ee17..3406bdd 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->mmc_clk)
sclk = host->mmc_clk(host->dev_index);
sclk = host->mmc_clk(host);Do you need to change dw_mmc_simple.c as well?
Not able to find any file dw_mmc_simple.c. Please do let me know if I need to check any file getting effected.
Regards, Simon