Hi Tom,
I've checked out the origin/master HEAD: SHA1: 225fd8c5d4556547896a5d32ee092a258f3df638
It turns out that the Exynos4 Trats serial console output is broken because of APLL clock frequency change.
Responsible change [*]: Exynos5: clock: Update the equation to calculate PLL output frequency SHA1: 234370cab4b2f096e095fe8f3284fd39740a4023
The above change is already at mainline (v2013.07-rc2)
Minkyu has provided a correction patch [**]: [U-Boot] [PATCH] arm: exynos: fix clock calculation
Unfortunately, this fixed the problem partially (and has been pulled by Albert already).
I've just sent the fix for the Exynos4210 based boards [***]: http://patchwork.ozlabs.org/patch/258775/ [U-Boot] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
The solution was tested at Exynos4210 Trats board.
I hope, that we will manage to fix things before final v2013.07 release.
Clock change is crucial, and I'm afraid that Minkyu and Rajeshwari will read this mail on Monday. Can we wait for final release until then?
For now, change [*] is at v2013.07, but fixes [**] and [***] aren't.
I would opt for giving the interested party time to test all three patches together before we release the final v2013.07.