At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename the PCH functions - Update the get_version() handle to use an enum - Add a function to obtain the SPI base address
drivers/pch/Makefile | 1 + drivers/pch/pch7.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/pch.h | 4 ++++ 3 files changed, 48 insertions(+) create mode 100644 drivers/pch/pch7.c
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index d69a99c..33aa727 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -3,3 +3,4 @@ #
obj-y += pch-uclass.o +obj-y += pch7.o diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000..4532223 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; diff --git a/include/pch.h b/include/pch.h index ef23570..b3f88bd 100644 --- a/include/pch.h +++ b/include/pch.h @@ -14,6 +14,10 @@ enum pch_version { PCHV_9, };
+enum { + PCH_RCBA = 0xf0, +}; + /* Operations for the Platform Controller Hub */ struct pch_ops { /**