From: Ye Li ye.li@nxp.com
Update DDR PHY settings to support LPDDR4 mode only by adjusting DQ VREF ctrl, ODT and pads drive strength.
Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/imx8ulp_evk/lpddr4_timing.c | 32 ++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c index 4546e92b01..09240999ce 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -701,7 +701,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e064154, 0x2000000 }, /* 85 */ { 0x2e064158, 0x51515042 }, /* 86 */ { 0x2e06415c, 0x31c06000 }, /* 87 */ - { 0x2e064160, 0x9bf000a }, /* 88 */ + { 0x2e064160, 0x6bf000a }, /* 88 */ { 0x2e064164, 0xc0c000 }, /* 89 */ { 0x2e064168, 0x1000000 }, /* 90 */ { 0x2e06416c, 0x10001000 }, /* 91 */ @@ -777,7 +777,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e064554, 0x2000000 }, /* 341 */ { 0x2e064558, 0x51515042 }, /* 342 */ { 0x2e06455c, 0x31c06000 }, /* 343 */ - { 0x2e064560, 0x9bf000a }, /* 344 */ + { 0x2e064560, 0x6bf000a }, /* 344 */ { 0x2e064564, 0xc0c000 }, /* 345 */ { 0x2e064568, 0x1000000 }, /* 346 */ { 0x2e06456c, 0x10001000 }, /* 347 */ @@ -854,7 +854,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e064954, 0x2000000 }, /* 597 */ { 0x2e064958, 0x51515042 }, /* 598 */ { 0x2e06495c, 0x31c06000 }, /* 599 */ - { 0x2e064960, 0x9bf000a }, /* 600 */ + { 0x2e064960, 0x6bf000a }, /* 600 */ { 0x2e064964, 0xc0c000 }, /* 601 */ { 0x2e064968, 0x1000000 }, /* 602 */ { 0x2e06496c, 0x10001000 }, /* 603 */ @@ -930,7 +930,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e064d54, 0x2000000 }, /* 853 */ { 0x2e064d58, 0x51515042 }, /* 854 */ { 0x2e064d5c, 0x31c06000 }, /* 855 */ - { 0x2e064d60, 0x9bf000a }, /* 856 */ + { 0x2e064d60, 0x6bf000a }, /* 856 */ { 0x2e064d64, 0xc0c000 }, /* 857 */ { 0x2e064d68, 0x1000000 }, /* 858 */ { 0x2e064d6c, 0x10001000 }, /* 859 */ @@ -1032,7 +1032,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e065860, 0x8040201 }, /* 1560 */ { 0x2e065864, 0x2010201 }, /* 1561 */ { 0x2e065868, 0xf0f0f }, /* 1562 */ - { 0x2e06586c, 0x241b42 }, /* 1563 */ + { 0x2e06586c, 0x241342 }, /* 1563 */ { 0x2e065874, 0x1020000 }, /* 1565 */ { 0x2e065878, 0x701 }, /* 1566 */ { 0x2e06587c, 0x54 }, /* 1567 */ @@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e0658a0, 0x4410 }, /* 1576 */ { 0x2e0658a4, 0x4410 }, /* 1577 */ { 0x2e0658b0, 0x60000 }, /* 1580 */ - { 0x2e0658b8, 0x96 }, /* 1582 */ + { 0x2e0658b8, 0x66 }, /* 1582 */ { 0x2e0658bc, 0x10000 }, /* 1583 */ { 0x2e0658c0, 0x8 }, /* 1584 */ { 0x2e0658d8, 0x3000000 }, /* 1590 */ @@ -1074,20 +1074,20 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = { { 0x2e065980, 0x300 }, /* 1632 */ { 0x2e065984, 0x300 }, /* 1633 */ { 0x2e065988, 0x300 }, /* 1634 */ - { 0x2e06598c, 0x4bf77 }, /* 1635 */ - { 0x2e065990, 0x77 }, /* 1636 */ - { 0x2e065994, 0x27f }, /* 1637 */ - { 0x2e06599c, 0x27f }, /* 1639 */ - { 0x2e0659a4, 0x27f00 }, /* 1641 */ + { 0x2e06598c, 0x337cc }, /* 1635 */ + { 0x2e065990, 0x8 }, /* 1636 */ + { 0x2e065994, 0x1b7 }, /* 1637 */ + { 0x2e06599c, 0x1b7 }, /* 1639 */ + { 0x2e0659a4, 0x1b700 }, /* 1641 */ { 0x2e0659a8, 0x1980000 }, /* 1642 */ - { 0x2e0659ac, 0x27fcc }, /* 1643 */ - { 0x2e0659b4, 0x27f00 }, /* 1645 */ + { 0x2e0659ac, 0x1b7cc }, /* 1643 */ + { 0x2e0659b4, 0x1b700 }, /* 1645 */ { 0x2e0659b8, 0x1980000 }, /* 1646 */ - { 0x2e0659bc, 0x27f00 }, /* 1647 */ + { 0x2e0659bc, 0x1b700 }, /* 1647 */ { 0x2e0659c0, 0x1980000 }, /* 1648 */ - { 0x2e0659c4, 0x27f00 }, /* 1649 */ + { 0x2e0659c4, 0x1b700 }, /* 1649 */ { 0x2e0659c8, 0x1980000 }, /* 1650 */ - { 0x2e0659cc, 0x27f00 }, /* 1651 */ + { 0x2e0659cc, 0x1b700 }, /* 1651 */ { 0x2e0659d0, 0x1980000 }, /* 1652 */ { 0x2e0659d4, 0x20040003 }, /* 1653 */ };