On 18.4.2016 09:08, Heiko Schocher wrote:
Hello Michal,
Am 14.04.2016 um 14:15 schrieb Michal Simek:
400kHz is maximum freq which can be used on Xilinx ZynqMP. Support it with standard divider calculator. Input freq is hardcoded to 100MHz input freq till we have clock driver which can provide this information for exact configuration.
Signed-off-by: Michal Simek michal.simek@xilinx.com
drivers/i2c/i2c-cdns.c | 76 +++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 7 deletions(-)
just some nitpick, beside of this:
Reviewed-by: Heiko Schocher hs@denx.de
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 0bc6aaaa6f90..5642cd91fe2e 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -112,6 +112,7 @@ static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
struct i2c_cdns_bus { int id;
- unsigned int input_freq; struct cdns_i2c_regs __iomem *regs; /* register base */ };
@@ -133,20 +134,79 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) return int_status & mask; }
+#define CDNS_I2C_DIVA_MAX 4 +#define CDNS_I2C_DIVB_MAX 64
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
unsigned int *a, unsigned int *b)+{
- unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
- unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
- unsigned int last_error, current_error;
- /* calculate (divisor_a+1) x (divisor_b+1) */
please add a space before and after the "+"
I have fixed this.
Thanks, Michal