Re: [U-Boot] [PATCH v8 1/8] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

On Wed, 2019-02-13 at 17:07 +0100, Marek Vasut wrote:

On 2/13/19 3:18 PM, tien.fong.chee@intel.com wrote:

...

From: Tien Fong Chee tien.fong.chee@intel.com

This patch adds description on properties about file name used for both peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

---

changes for v8

• Removed explanation about support for altr,bitstream-core

changes for v7

• Provided example of setting FPGA FIT image for both early IO

release   and full release FPGA configuration.

---

.../fpga/altera-socfpga-a10-fpga-mgr.txt           | 26 +++++++++++++++++++++-  1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga- mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga- mgr.txt index 2fd8e7a..da210bf 100644 --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -7,8 +7,31 @@ Required properties:                 - The second index is for writing FPGA configuration data.  - resets     : Phandle and reset specifier for the device's reset.  - clocks     : Clocks used by the device. +- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,

•    FPGA core bitstream and full bitstream.
  

So the file contains three bitstreams ? I thought we can load only the core here.

Here is for telling FPGA driver which fitImage file gonna be processed. You can put whatever bitstreams in fitImage. Then, in the default configuration, you can tell SPL FPGA driver program which bitstream, it could be both periph.rbf and core.rbf or just programming periph.rbf only.

...

-Example:

•    Full bitstream, consist of peripheral bitstream
  

and core

•    bitstream.
  

•    FPGA peripheral bitstream is used to initialize
  

FPGA IOs,

•    PLL, IO48 and DDR. This bitstream is required
  

to get DDR up

•    running.
  

•    FPGA core bitstream contains FPGA design which
  

is used to

•    program FPGA CRAM and ERAM.
  

+Example: Bundles both peripheral bitstream and core bitstream into FIT image

• called fit_spl_fpga.itb. This FIT image can be created

through running

• this command: tools/mkimage

•        -E -p 400
  

Is the padding still required ?

Yes, i think that padding method should be sufficient for all use cases, i guess both NAND and QSPI may need this also.

You want me to support data offset(without padding) also?

...

•        -f board/altera/arria10-
  

socdk/fit_spl_fpga.its

•        fit_spl_fpga.itb
  

• For details of describing structure and contents of the

FIT image,

• please refer board/altera/arria10-socdk/fit_spl_fpga.its

+- Examples for booting with full release or booting with early IO release, then +  follow by entering early user mode:     fpga_mgr: fpga-mgr@ffd03000 {   compatible = "altr,socfpga-a10-fpga-mgr"; @@ -16,4 +39,5 @@ Example:          0xffcfe400 0x20>;   clocks = <&l4_mp_clk>;   resets = <&rst FPGAMGR_RESET>;

• altr,bitstream = "fit_spl_fpga.itb";
  

};