On 01/17/2019 11:39 AM, Anup Patel wrote:
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra wesley@sifive.com found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed board.
Signed-off-by: Paul Walmsley paul.walmsley@sifive.com Signed-off-by: Atish Patra atish.patra@wdc.com Signed-off-by: Anup Patel anup.patel@wdc.com
Can't say much about how the device works or whether this is in 100% compliance to the U-Boot clk framework, but I didn't see anything obviously wrong :).
Reviewed-by: Alexander Graf agraf@suse.de
Alex