The gmac for integrated phy need 50M clock, it seems that only come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + drivers/clk/rockchip/clk_rk322x.c | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index a7999ca..801363d 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -13,6 +13,7 @@
#define APLL_HZ (600 * MHz) #define GPLL_HZ (594 * MHz) +#define CPLL_HZ (600 * MHz)
#define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000 diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 72c8757..4022065 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -40,6 +40,7 @@ enum { /* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -89,11 +90,13 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | - APLL_MODE_SLOW << APLL_MODE_SHIFT); + APLL_MODE_SLOW << APLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
/* init pll */ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
/* * select apll as cpu/core clock pll source and @@ -166,7 +169,8 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | - APLL_MODE_NORM << APLL_MODE_SHIFT); + APLL_MODE_NORM << APLL_MODE_SHIFT | + CPLL_MODE_NORM << CPLL_MODE_SHIFT); }
/* Get pll rate by id */ @@ -258,8 +262,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else - /* CPLL is not set */ - return -EPERM; + pll_rate = CPLL_HZ;
div = DIV_ROUND_UP(pll_rate, freq) - 1; if (div <= 0x1f)