Enable the am625 instruction cache on SPL and U-boot earlier for the A53 to execute code a bit faster. For normal boot flow, it was possible to gain about 2 seconds on boot time.
Signed-off-by: Joao Paulo Goncalves joao.goncalves@toradex.com --- Hello all,
We are trying to optimize boot time on our AM62 devices and on TI community forum [1] someone advised to enable ICACHE for am625. We enabled it, tested and got around 2 seconds faster boot on storage media and about 5 seconds with DFU for downloading images from A53 SPL. However, we don't know if this is the correct solution and want more comments on this or why the ICACHE was not enabled by TI in the first place.
[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/12...
Regards, Joao Paulo Goncalves
arch/arm/mach-k3/am625_init.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 8fa36f7b91..d665d07b0b 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -210,6 +210,9 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } spl_enable_dcache(); + + if (!IS_ENABLED(CONFIG_CPU_V7R) && !IS_ENABLED(CONFIG_SYS_ICACHE_OFF)) + icache_enable(); }
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)