On 03/01/2018 11:36 PM, Hannes Schmelzer wrote:
Some IP-core implementations of the SDHCI have different troubles on the silicon where they are placed.
On ZYNQ platform for example Xilinx doesn't accept the hold timing of an eMMC chip which operates in High-Speed mode. Due to this fact the "SDHCI_QUIRK_NO_HISPD_BIT" quirk was born.
This commit reflects this fact within the host-controller capabilities, so that the layer above (mmc-driver) can setup the card correctly.
Otherwise the MMC card will be switched into high-speed mode and causes possible timing violation on the host-controller side.
Signed-off-by: Hannes Schmelzer oe5hpm@oevsv.at
SDHCI_QUIRK_NO_HISPD_BIT had added because of Samsung SoC. (I had added this quirk, so i know exactly what purpose.) Samsung SoC didn't use the SDHCI_CTRL_HISPD bit at HOST_CNOTROL register. Instead, its bit is used to other purpose.
NACK.
Best Regards, Jaehoon Chung
drivers/mmc/sdhci.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index d31793a..defe6db 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -602,6 +602,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_8BIT; }
- if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) {
cfg->host_caps &= ~MMC_MODE_HS;cfg->host_caps &= ~MMC_MODE_HS_52MHz;- }
- if (host->host_caps) cfg->host_caps |= host->host_caps;