13 Mar
2015
13 Mar
'15
3:30 p.m.
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states that:
0: L1 & L2 cached 4: L2 cache coherent (non allocaing) 8: L2 cached only c: Direct uncached.
Caches aren't working on BCM2xxx or what's the reason for this hack ? Or are these different (not on-CPU) caches we're talking about (yes, I did notice the GPU Lx cache stuff)?
Best regards, Marek Vasut