18 Sep
2020
18 Sep
'20
4:06 p.m.
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut marex@denx.de Cc: Eric Nelson eric@nelint.com Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Stefano Babic sbabic@denx.de Reviewed-by: Fabio Estevam festevam@gmail.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
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