This patch adds support for the PDU001 board.
Signed-off-by: Felix Brack fb@ltec.ch ---
Changes in v2: - use DT to configure the board - use new single-register pin controller - use new TPS65910 PMIC driver - eliminate the need of CONFIG_DM_I2C_COMPAT, i.e. use DM for i2c - clarify the function of the 'Run LED' - fix ordering of include files - replace deprecated SPDX license identifiers
arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/am335x-pdu001.dts | 612 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/am33xx/Kconfig | 9 + board/eets/pdu001/Kconfig | 66 ++++ board/eets/pdu001/MAINTAINERS | 6 + board/eets/pdu001/Makefile | 13 + board/eets/pdu001/README | 35 +++ board/eets/pdu001/board.c | 276 +++++++++++++++++ board/eets/pdu001/board.h | 38 +++ board/eets/pdu001/mux.c | 120 ++++++++ configs/am335x_pdu001_defconfig | 55 ++++ include/configs/pdu001.h | 87 ++++++ 13 files changed, 1320 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/am335x-pdu001.dts create mode 100644 board/eets/pdu001/Kconfig create mode 100644 board/eets/pdu001/MAINTAINERS create mode 100644 board/eets/pdu001/Makefile create mode 100644 board/eets/pdu001/README create mode 100644 board/eets/pdu001/board.c create mode 100644 board/eets/pdu001/board.h create mode 100644 board/eets/pdu001/mux.c create mode 100644 configs/am335x_pdu001_defconfig create mode 100644 include/configs/pdu001.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f6d57f5..15349b3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1339,6 +1339,7 @@ source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" source "board/zipitz2/Kconfig" +source "board/eets/pdu001/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9540ba4..02b3c36 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -161,7 +161,8 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-bonegreen.dtb \ am335x-icev2.dtb \ am335x-pxm50.dtb \ - am335x-rut.dtb + am335x-rut.dtb \ + am335x-pdu001.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts new file mode 100644 index 0000000..0967e82 --- /dev/null +++ b/arch/arm/dts/am335x-pdu001.dts @@ -0,0 +1,612 @@ +/* + * pdu001.dts + * + * EETS GmbH PDU001 board device tree file + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/leds-pca9532.h> + +/ { + model = "EETS,PDU001"; + compatible = "eets,pdu001", "ti,am33xx"; + + chosen { + stdout-path = &uart3; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_s0>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + 240x320p16 { + clock-frequency = <6500000>; + hactive = <240>; + vactive = <320>; + hfront-porch = <6>; + hback-porch = <6>; + hsync-len = <1>; + vback-porch = <6>; + vfront-porch = <6>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + de-active = <0>; + }; + }; + }; + + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&l4_wkup { + u-boot,dm-pre-reloc; +}; + +&scm { + u-boot,dm-pre-reloc; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + u-boot,dm-pre-reloc; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ + AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + >; + u-boot,dm-pre-reloc; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Port 1 (emac0) */ + AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ + AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */ + AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */ + AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + + /* Port 2 (emac1) */ + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */ + AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */ + AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */ + AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ + AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ + AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ + AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */ + AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */ + AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + /* eMMC */ + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + >; + u-boot,dm-pre-reloc; + }; + + mmc2_pins: pinmux_mmc2_pins { + /* SD cardcage */ + pinctrl-single,pins = < + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + /* card change signal for frontpanel SD cardcage */ + AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + >; + u-boot,dm-pre-reloc; + }; + + lcd_pins_s0: lcd_pins_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <0 0>; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + u-boot,dm-pre-reloc; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + m2_eeprom: m2_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + board_24aa025e48: board_24aa025e48@50 { + compatible = "microchip,24aa025e48"; + reg = <0x50>; + }; + + backplane_24aa025e48: backplane_24aa025e48@53 { + compatible = "microchip,24aa025e48"; + reg = <0x53>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + reg = <0x60>; + psc0 = <0x97>; + pwm0 = <0x80>; + psc1 = <0x97>; + pwm1 = <0x10>; + + run.red@0 { + type = <PCA9532_TYPE_LED>; + }; + run.green@1 { + type = <PCA9532_TYPE_LED>; + default-state = "on"; + }; + s2.red@2 { + type = <PCA9532_TYPE_LED>; + }; + s2.green@3 { + type = <PCA9532_TYPE_LED>; + }; + s1.yellow@4 { + type = <PCA9532_TYPE_LED>; + }; + s1.green@5 { + type = <PCA9532_TYPE_LED>; + }; + }; + + pca9530: pca9530@61 { + compatible = "nxp,pca9530"; + reg = <0x61>; + + tft-panel@0 { + type = <PCA9532_TYPE_LED>; + linux,default-trigger = "backlight"; + default-state = "on"; + }; + }; + + mcp79400: mcp79400@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + cfaf240320a032t { + compatible = "orise,otm3225a"; + reg = <0>; + spi-max-frequency = <1000000>; + // SPI mode 3 + spi-cpol; + spi-cpha; + status = "okay"; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* + * Disable soc's rtc as we have no VBAT for it. This makes the board + * rtc (Microchip MCP79400) the default rtc device 'rtc0'. + */ +&rtc { + status = "disabled"; +}; + +&lcdc { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-name = "ldo_vrtc"; + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-name = "buck_vdd_ddr"; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits */ + regulator-name = "buck_vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits */ + regulator-name = "buck_vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-name = "boost_res"; + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "ldo_vdig1"; + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-name = "ldo_vdig2"; + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-name = "ldo_vpll"; + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-name = "ldo_vdac"; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-name = "ldo_vaux1"; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-name = "ldo_vaux2"; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-name = "ldo_vaux33"; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-name = "ldo_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vbb_reg: regulator@13 { + regulator-name = "bat_vbb"; + }; + }; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + dual_emac; /* no switch, two distinct MACs */ + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x01 0x10 0x22 0x33>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + non-removable; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 7260d27..9a9ccd7 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -185,6 +185,15 @@ config TARGET_THUBAN select DM_SERIAL select DM_GPIO
+config TARGET_PDU001 + bool "Support PDU001" + select DM + select DM_SERIAL + help + Support for PDU001 platform developed by EETS GmbH. + The PDU001 is a processor and display unit developed around + the Computing-Module m2 from bytes at work AG. + endchoice
endif diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig new file mode 100644 index 0000000..ba44900 --- /dev/null +++ b/board/eets/pdu001/Kconfig @@ -0,0 +1,66 @@ +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +if TARGET_PDU001 + +config SYS_BOARD + default "pdu001" + +config SYS_VENDOR + default "eets" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pdu001" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 4 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. The best choice for the + PDU001 is UART3 as it is wired to the header K2; enter 4 here to + use UART3. UART0 is connected to the EIA-485 transceiver. If you + really need to use it, you are advised to remove the transceiver U14 + from the board. UART1 is wired to the backplane and therefore + accessible from there or by the backplane connector K1 of the PDU. + Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or + UART0 (enter 1 here) are not sensible since they are not wired to + any connector and therefore difficult to access. + +choice + prompt "State of Run LED" + default PDU001_RUN_LED_RED + help + The PDU001 has a bi-color (red/green) LED labeled 'Run' which + can be used to indicate the operating state of the board. By + default it will be lit red by U-Boot. Later in the start-up + process it can be changed to green (or heartbeat or anything else) + by the kernel or some other software. + +config RUN_LED_RED + bool + prompt "Red" + help + Lit Run LED red. + +config RUN_LED_GREEN + bool + prompt "Green" + help + Lit Run LED green. + +config RUN_LED_OFF + bool + prompt "Off" + help + Do not lit Run LED. + +endchoice + +endif diff --git a/board/eets/pdu001/MAINTAINERS b/board/eets/pdu001/MAINTAINERS new file mode 100644 index 0000000..fbd47cf --- /dev/null +++ b/board/eets/pdu001/MAINTAINERS @@ -0,0 +1,6 @@ +PDU001 BOARD +M: Felix Brack fb@ltec.ch +S: Maintained +F: board/eets/pdu001/ +F: include/configs/pdu001.h +F: configs/pdu001_defconfig diff --git a/board/eets/pdu001/Makefile b/board/eets/pdu001/Makefile new file mode 100644 index 0000000..2f2661d --- /dev/null +++ b/board/eets/pdu001/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README new file mode 100644 index 0000000..3592d5c --- /dev/null +++ b/board/eets/pdu001/README @@ -0,0 +1,35 @@ +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +Summary +======= + +This document covers the PDU001 target. + +Hardware +======== + +The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is +manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2 +SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on +AM3352 SOC from TI (http://www.ti.com). + +Customization +============= + +As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice +is 4 here since UART3 is wired to the connector K2. +The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED +or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn +off the Run LED. + +Booting +======= + +The system boots from either eMMC or SD card cage. It will first try to boot +from the SD card cage. If this fails (missing or unbootable SD card) it will +try to boot from the internal eMMC. The root file system is always expected to +be located in the second partition of the device (eMMC or SD card) that pro- +vided the boot loader. diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c new file mode 100644 index 0000000..756e97a --- /dev/null +++ b/board/eets/pdu001/board.c @@ -0,0 +1,276 @@ +/* + * board.c + * + * Board functions for EETS PDU001 board + * + * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/ + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <i2c.h> +#include <environment.h> +#include <watchdog.h> +#include <debug_uart.h> +#include <dm/ofnode.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_ADDR_NODE_ID 0x50 +#define I2C_REG_NODE_ID_BASE 0xfa +#define NODE_ID_BYTE_COUNT 6 + +#define I2C_ADDR_LEDS 0x60 +#define I2C_REG_RUN_LED 0x06 +#define RUN_LED_OFF 0x0 +#define RUN_LED_RED 0x1 +#define RUN_LED_GREEN (0x1 << 2) + +#define VDD_MPU_REGULATOR "regulator@2" +#define VDD_CORE_REGULATOR "regulator@3" +#define DEFAULT_CORE_VOLTAGE 1137500 + +/* + * boot device save register + * ------------------------- + * The boot device can be quired by 'spl_boot_device()' in + * 'am33xx_spl_board_init'. However it can't be saved in the u-boot + * environment here. In turn 'spl_boot_device' can't be called in + * 'board_late_init' which allows writing to u-boot environment. + * To get the boot device from 'am33xx_spl_board_init' to + * 'board_late_init' we therefore use a scratch register from the RTC. + */ +#define CONFIG_SYS_RTC_SCRATCH0 0x60 +#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0) + +#ifdef CONFIG_SPL_BUILD +static void save_boot_device(void) +{ + *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device(); +} +#endif + +u32 boot_device(void) +{ + return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)); +} + +/* Store the boot device in the environment variable 'boot_device' */ +static void env_set_boot_device(void) +{ + switch (boot_device()) { + case BOOT_DEVICE_MMC1: { + env_set("boot_device", "emmc"); + break; + } + case BOOT_DEVICE_MMC2: { + env_set("boot_device", "sdcard"); + break; + } + default: { + env_set("boot_device", "unknown"); + break; + } + } +} + +static void set_run_led(struct udevice *dev) +{ + int val = RUN_LED_OFF; + + if (IS_ENABLED(CONFIG_RUN_LED_RED)) + val = RUN_LED_RED; + else if (IS_ENABLED(CONFIG_RUN_LED_GREEN)) + val = RUN_LED_GREEN; + + dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val); +} + +/* Set 'serial#' to the EUI-48 value of board node ID chip */ +static void env_set_serial(struct udevice *dev) +{ + int val; + char serial[2 * NODE_ID_BYTE_COUNT + 1]; + int n; + + for (n = 0; n < sizeof(serial); n += 2) { + val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2); + sprintf(serial + n, "%02X", val); + } + serial[2 * NODE_ID_BYTE_COUNT] = '\0'; + env_set("serial#", serial); +} + +static void set_mpu_and_core_voltage(void) +{ + int mpu_vdd; + int sil_rev; + struct udevice *dev; + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + /* + * The PDU001 (more precisely the computing module m2) uses a + * TPS65910 PMIC. For all MPU frequencies we support we use a CORE + * voltage of 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + + /* + * Depending on MPU clock and PG we will need a different VDD + * to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m); + + /* first update the MPU voltage */ + if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) { + if (regulator_set_value(dev, mpu_vdd)) + debug("failed to set MPU voltage\n"); + } else { + debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR); + } + + /* second update the CORE voltage */ + if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) { + if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE)) + debug("failed to set CORE voltage\n"); + } else { + debug("invalid CORE voltage ragulator %s\n", + VDD_CORE_REGULATOR); + } +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +static const struct ddr_data ddr2_data = { + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = MT47H128M16RT25E_RATIO, + .cmd1csratio = MT47H128M16RT25E_RATIO, + .cmd2csratio = MT47H128M16RT25E_RATIO, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, +}; + +#define OSC (V_OSCK / 1000000) +const struct dpll_params dpll_ddr = { + 266, OSC - 1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC - 1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC - 1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + + /* save boot device for later use by 'board_late_init' */ + save_boot_device(); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr; +} + +void set_mux_conf_regs(void) +{ + /* done first by the ROM and afterwards by the pin controller driver */ + enable_i2c0_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(266, &ioregs, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); +} +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifdef CONFIG_DEBUG_UART +void board_debug_uart_init(void) +{ + /* done by pin controller driver if not debugging */ + enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + struct udevice *dev; + + set_mpu_and_core_voltage(); + env_set_boot_device(); + + /* second I2C bus connects to node ID and front panel LED chip */ + if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev)) + set_run_led(dev); + if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev)) + env_set_serial(dev); + + return 0; +} +#endif diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h new file mode 100644 index 0000000..3332560 --- /dev/null +++ b/board/eets/pdu001/board.h @@ -0,0 +1,38 @@ +/* + * board.h + * + * EETS GmbH PDU001 board information header + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We have two pin mux functions that must exist. First we need I2C0 to + * access the TPS65910 PMIC located on the M2 computing module. + * Second, if we want low-level debugging or a early UART (ie. before the + * pin controller driver is running), we need one of the UART ports UART0 to + * UART5 (usually UART3 since it is wired to K2). + * In case of I2C0 access we explicitly don't rely on the the ROM but we could + * do so as we use the primary mode (mode 0) for I2C0. + * All other multiplexing and pin configuration is done by the DT once it + * gets parsed by the pin controller driver. + * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well + * as MMC1 (microSD card-cage) since these are our boot devices. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_uart_pin_mux(u32 addr); +void enable_i2c0_pin_mux(void); + +#endif diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c new file mode 100644 index 0000000..1c2b1b0 --- /dev/null +++ b/board/eets/pdu001/mux.c @@ -0,0 +1,120 @@ +/* + * mux.c + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_uart_pin_mux(u32 addr) +{ + switch (addr) { + case CONFIG_SYS_NS16550_COM1: + enable_uart0_pin_mux(); + break; + case CONFIG_SYS_NS16550_COM2: + enable_uart1_pin_mux(); + break; + case CONFIG_SYS_NS16550_COM3: + enable_uart2_pin_mux(); + break; + case CONFIG_SYS_NS16550_COM4: + enable_uart3_pin_mux(); + break; + case CONFIG_SYS_NS16550_COM5: + enable_uart4_pin_mux(); + break; + case CONFIG_SYS_NS16550_COM6: + enable_uart5_pin_mux(); + break; + } +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig new file mode 100644 index 0000000..31312b2 --- /dev/null +++ b/configs/am335x_pdu001_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y +CONFIG_TARGET_PDU001=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" +CONFIG_LOCALVERSION="-EETS-1.0.0" +CONFIG_BOOTDELAY=1 +CONFIG_SPL=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_SDHCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_TPS65910=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS65910=y +CONFIG_SYS_NS16550=y +# CONFIG_USE_TINY_PRINTF is not set +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h new file mode 100644 index 0000000..e8d87e2 --- /dev/null +++ b/include/configs/pdu001.h @@ -0,0 +1,87 @@ +/* + * pdu001.h + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __CONFIG_PDU001_H +#define __CONFIG_PDU001_H + +#include <configs/ti_am335x_common.h> + +/* No more need for I2C legacy compatibility for this board. + * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there + * for the right moment to delete the following line. + */ +#undef CONFIG_DM_I2C_COMPAT + +/* Using 32K of volatile storage for environment */ +#define CONFIG_ENV_SIZE 0x4000 + +#define MACH_TYPE_PDU001 5075 +#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#if CONFIG_CONS_INDEX == 1 + #define CONSOLE_DEV "ttyO0" +#elif CONFIG_CONS_INDEX == 2 + #define CONSOLE_DEV "ttyO1" +#elif CONFIG_CONS_INDEX == 3 + #define CONSOLE_DEV "ttyO2" +#elif CONFIG_CONS_INDEX == 4 + #define CONSOLE_DEV "ttyO3" +#elif CONFIG_CONS_INDEX == 5 + #define CONSOLE_DEV "ttyO4" +#elif CONFIG_CONS_INDEX == 6 + #define CONSOLE_DEV "ttyO5" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run eval_boot_device;" \ + "setenv bootargs console=${console} " \ + "vt.global_cursor_default=0 " \ + "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \ + "rootfstype=ext4 " \ + "rootwait " \ + "rootdelay=1;" \ + "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \ + "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \ + "bootz ${loadaddr} - ${fdtaddr}" + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "fdtfile=am335x-pdu001.dtb\0" \ + "bootfile=zImage\0" \ + "console=" CONSOLE_DEV ",115200n8\0" \ + "root_fs_partition=2\0" \ + "eval_boot_device=" \ + "if test $boot_device = emmc; then " \ + "setenv mmc_boot 0;" \ + "elif test $boot_device = sdcard; then " \ + "setenv mmc_boot 1;" \ + "else " \ + "echo Bootdevice is neither MMC0 nor MMC1;" \ + "reset;" \ + "fi;" \ + "\0" +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 UART2_BASE +#define CONFIG_SYS_NS16550_COM4 UART3_BASE +#define CONFIG_SYS_NS16550_COM5 UART4_BASE +#define CONFIG_SYS_NS16550_COM6 UART5_BASE +#define CONFIG_BAUDRATE 115200 + +#endif /* ! __CONFIG_PDU001_H */