18 Dec
2008
18 Dec
'08
8:15 a.m.
+void board_init_f(ulong bootflag) +{
- volatile ccsr_local_ecm_t *ecm = (void *)
(CONFIG_SYS_MPC85xx_ECM_ADDR);
- u32 mas0, mas1, mas2, mas3;
- /* init serial port */
- NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500),
get_bus_clk() / 16 / CONFIG_BAUDRATE);- puts("NAND boot... ");
- init_timebase();
- /* set TLB1[8] for DDR mapping */
- mas0 = FSL_BOOKE_MAS0(1, 8, 0);
- mas1 = FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G);
- mas2 = FSL_BOOKE_MAS2(0, 0);
- mas3 = FSL_BOOKE_MAS3(0, 0, MAS3_SX | MAS3_SW | MAS3_SR);
- tlb_set(mas0, mas1, mas2, mas3);
- /* set LAW0 for DDR access */
- out_be32(&ecm->lawbar0, 0);
- out_be32(&ecm->lawar0, LAWAR_EN | (LAW_TRGT_IF_DDR << 20)
| LAW_SIZE_512M);we should use the last law not the first one in general.
The last law is also good choice, I want to make better way to handle the LAW.
- /* init DDR memory controller */
- fixed_sdram();
- /* relocate the first bootstrap */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000,
(gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);+}
+void board_init_r(gd_t *gd, ulong dest_addr) +{
- nand_boot();
+}
This code is part of the first stage (first 4k?) or second stage loader?
The first stage(first 4K)
what is the entry point of the second stage loader?
_start_e500.