From: Lad, Prabhakar prabhakar.lad@ti.com
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in sync with the timings used in Linux. Linux is configuring the timing register as 0x08222204, where as currently it configured to 0x00100084 in U-Boot. This issue was found out when support for NAND SPL is added in U-Boot. Without this patch U-Boot does not come up with SPL.
Signed-off-by: Lad, Prabhakar prabhakar.lad@ti.com Signed-off-by: Rajashekhara, Sudhakar sudhakar.raj@ti.com Signed-off-by: Hadli, Manjunath manjunath.hadli@ti.com --- Changes for v3: 1: Patch number chnaged due to patch 6 split up of previous version.
board/davinci/da8xxevm/da850evm.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 0d75b84..1c0f75d 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -348,11 +348,11 @@ int board_init(void) * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT),