Hello Vladimir,
On Tue, 14 Jul 2015 23:23:57 +0300, Vladimir Zapolskiy vz@mleia.com wrote:
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine.
The driver can be included to an SPL image.
This is needed for an upcoming new board support patch, right? If so, then I suggest you put together all patches for this new board in a single series. This will make it clear(er) you're not adding dead code here.
Signed-off-by: Vladimir Zapolskiy vz@mleia.com Cc: Albert ARIBAUD albert.u.boot@3adev.fr
Amicalement,