+Suresh Gupta
On 06/21/2016 12:22 AM, Sriram Dash wrote:
Modifies errata implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Also, Adds errata for P1010 and P2041 2.0.
It would be helpful to mention erratum number A-006261 in the commit message in case you need to find this commit later.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 ++-- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 2 ++ drivers/usb/common/fsl-errata.c | 6 ++++-- 4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 61f5639..61dedfc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -114,10 +114,10 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) setbits_be32(&usb_phy->config2, CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
- temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
- temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
- temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
- temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
Has this been wrong all the time? If the disconnect voltage threshold was wrong, did someone observe abnormal behavior?
Suresh, please comment here.
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); #endif } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 505d355..9b7feda 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -162,6 +162,7 @@ #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
Enabling the workaround for another SoC should be in a separated patch.
#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c045a24..07ad22d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2953,6 +2953,8 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index ebe60a8..a69b977 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -53,7 +53,8 @@ bool has_erratum_a006261(void) case SVR_P2041: case SVR_P2040: return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
IS_SVR_REV(svr, 1, 1) ||IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);@@ -72,7 +73,8 @@ bool has_erratum_a006261(void) case SVR_T2081: return IS_SVR_REV(svr, 1, 0); case SVR_P5040:
return IS_SVR_REV(svr, 1, 0);
return IS_SVR_REV(svr, 1, 0) ||IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
Are you sure this erratum applies to P5040 rev 2.0 and rev 2.1? My document shows it doesn't (only applies to rev 1.0).
York