Am 15.03.2019 um 22:20 schrieb Marek Vasut:
On 3/15/19 8:44 PM, Simon Goldschmidt wrote:
To boot from fpga on socfpga gen5, we need to set CONFIG_SPL_TEXT_BASE to 0xC0000000 (hps2fpgaslaves base address).
Since converting CONFIG_SPL_TEXT_BASE to Kconfig hasn't been successful so far, let's make this value overridable in socfpga_common.h, so that we can have different board configs override this in socfpga_common.h.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Is this a fix for current release or new feature for next ?
Yes, it's a fix for the current release. It's the only thing missing to *finally* get mainline SPL booting from FPGA (on socfpga gen5).
As written in the log, the original plan was to move CONFIG_SPL_TEXT_BASE to Kconfig completely, but that didn't work out (still), which is why we have to do it in a different way.
I could provide a new board config to boot from FPGA if you want, but that did not make much sense to me as the FPGA image would be missing...
Regards, Simon
include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 181af9b646..191204b27b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -248,8 +248,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#ifndef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */