
On Tue, Jun 26, 2018 at 7:54 PM, Lothar Felten lothar.felten@gmail.com wrote:
Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins.
Signed-off-by: Lothar Felten lothar.felten@gmail.com
Changelog: new in v2 v2 -> v3 omit syscon node for R40 v3 -> v4 remove phy-mode from gmac node
arch/arm/dts/sun8i-r40.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 0aa76a2f10..3a0b3ab543 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -52,6 +52,7 @@ interrupt-parent = <&gic>;
aliases {
ethernet0 = &gmac; }; chosen {
@@ -161,6 +162,15 @@ #interrupt-cells = <3>; #gpio-cells = <3>;
gmac_pins_rgmii: gmac_rgmii {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA10",
"PA11", "PA12", "PA13",
"PA15", "PA16";
function = "gmac";
};
i2c0_pins: i2c0_pins { pins = "PB0", "PB1"; function = "i2c0";
@@ -202,6 +212,26 @@ #size-cells = <0>; };
gmac: ethernet@01c50000 {
compatible = "allwinner,sun8i-r40-gmac";
reg = <0x01c50000 0x2000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&osc24M>, <&osc24M>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
Where did this second clock come from?
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
Also, please have the new nodes match what is in the Linux kernel's device tree. This would make it easier to sync up without differences scattered all over.
ChenYu
gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>,
-- 2.14.1