[U-Boot] [PATCH v3 1/6] powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

11 Jun 2013

From: Dirk Eibach eibach@gdsys.de
A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.
Thanks to Wolfgang Denk for getting this sorted properly.
Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc
---
Changes in v3:
- squashed with "Add generic accessor functions for gdsys FPGA"
- strictly replace base address plus offset with  proper C structs
Changes in v2: None
board/gdsys/405ep/405ep.c        | 20 +++++------
 board/gdsys/405ep/dlvision-10g.c | 32 +++++++++++++----
 board/gdsys/405ep/io.c           | 30 ++++++++++++----
 board/gdsys/405ep/iocon.c        | 37 ++++++++++++++++----
 board/gdsys/405ep/neo.c          | 27 ++++++++++++---
 board/gdsys/405ex/405ex.c        | 20 +++++------
 board/gdsys/405ex/io64.c         | 48 +++++++++++++++++---------
 board/gdsys/common/osd.c         | 74 +++++++++++++++++++++++-----------------
 include/configs/dlvision-10g.h   |  4 +++
 include/configs/io.h             |  3 ++
 include/configs/io64.h           |  4 +++
 include/configs/iocon.h          |  3 ++
 include/configs/neo.h            |  3 ++
 include/gdsys_fpga.h             | 43 ++++++++++++++++++-----
 14 files changed, 247 insertions(+), 101 deletions(-)

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 6221171..4553a39 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -106,23 +106,21 @@ int board_early_init_r(void)
    gd405ep_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		struct ihs_fpga *fpga =
-			(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-		u16 *reflection_target = &fpga->reflection_low;
-#else
-		u16 *reflection_target = &fpga->reflection_high;
-#endif
    	/*
    	 * wait for fpga out of reset
    	 */
    	ctr = 0;
    	while (1) {
-			out_le16(&fpga->reflection_low,
-				REFLECTION_TESTPATTERN);
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-			if (in_le16(reflection_target) ==
-				REFLECTION_TESTPATTERN_INV)
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+			FPGA_GET_REG(k, reflection_low, &val);
+#else
+			FPGA_GET_REG(k, reflection_high, &val);
+#endif
+			if (val == REFLECTION_TESTPATTERN_INV)
    			break;
udelay(100000);
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 644493b..332d82f 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -71,6 +71,22 @@ enum {
    RAM_DDR2_64 = 2,
 };
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
    /* startup fans */
@@ -95,10 +111,9 @@ static unsigned int get_mc2_present(void)
static void print_fpga_info(unsigned dev)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
    unsigned unit_type;
    unsigned hardware_version;
    unsigned feature_rs232;
@@ -112,6 +127,10 @@ static void print_fpga_info(unsigned dev)
printf("FPGA%d: ", dev);
+	FPGA_GET_REG(dev, versions, &versions);
+	FPGA_GET_REG(dev, fpga_version, &fpga_version);
+	FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
    hardware_version = versions & 0x000f;
if (fpga_state
@@ -263,8 +282,9 @@ int checkboard(void)
int last_stage_init(void)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	u16 versions = in_le16(&fpga->versions);
+	u16 versions;
+
+	FPGA_GET_REG(0, versions, &versions);
print_fpga_info(0);
    if (get_mc2_present())
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 070dcbb..05707c4 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -53,6 +53,22 @@ enum {
    HWVER_122 = 3,
 };
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
    /* startup fans */
@@ -117,15 +133,18 @@ int checkboard(void)
static void print_fpga_info(void)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
    unsigned unit_type;
    unsigned hardware_version;
    unsigned feature_channels;
    unsigned feature_expansion;
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
    unit_type = (versions & 0xf000) >> 12;
    hardware_version = versions & 0x000f;
    feature_channels = fpga_features & 0x007f;
@@ -179,7 +198,6 @@ static void print_fpga_info(void)
  */
 int last_stage_init(void)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
    unsigned int k;
print_fpga_info();
@@ -191,7 +209,7 @@ int last_stage_init(void)
    	configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
-	out_le16(&fpga->quad_serdes_reset, 0);
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
return 0;
 }
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 0fc7db2..a531e5d 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -69,6 +69,22 @@ enum {
    RAM_DDR2_32 = 0,
 };
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
 /*
  * Check Board Identity:
  */
@@ -92,10 +108,9 @@ int checkboard(void)
static void print_fpga_info(void)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
    unsigned unit_type;
    unsigned hardware_version;
    unsigned feature_compression;
@@ -106,6 +121,10 @@ static void print_fpga_info(void)
    unsigned feature_carriers;
    unsigned feature_video_channels;
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
    unit_type = (versions & 0xf000) >> 12;
    hardware_version = versions & 0x000f;
    feature_compression = (fpga_features & 0xe000) >> 13;
@@ -230,17 +249,21 @@ int last_stage_init(void)
  */
 void fpga_gpio_set(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
+	FPGA_SET_REG(0, gpio.set, pin);
 }
void fpga_gpio_clear(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
+	FPGA_SET_REG(0, gpio.clear, pin);
 }
int fpga_gpio_get(int pin)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
+	u16 val;
+
+	FPGA_GET_REG(0, gpio.read, &val);
+
+	return val & pin;
 }
void gd405ep_init(void)
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
index d336e55..6de782b 100644
--- a/board/gdsys/405ep/neo.c
+++ b/board/gdsys/405ep/neo.c
@@ -44,6 +44,22 @@ enum {
    HWVER_300 = 3,
 };
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
    /* startup fans */
@@ -70,10 +86,9 @@ int checkboard(void)
static void print_fpga_info(void)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
    int fpga_state = get_fpga_state(0);
    unsigned unit_type;
    unsigned hardware_version;
@@ -90,6 +105,10 @@ static void print_fpga_info(void)
    	return;
    }
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
    unit_type = (versions & 0xf000) >> 12;
    hardware_version = versions & 0x000f;
    feature_channels = fpga_features & 0x007f;
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 32e24c0..339a3d0 100644
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -220,23 +220,21 @@ int board_early_init_r(void)
    gd405ex_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		struct ihs_fpga *fpga =
-			(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-		u16 *reflection_target = &fpga->reflection_low;
-#else
-		u16 *reflection_target = &fpga->reflection_high;
-#endif
    	/*
    	 * wait for fpga out of reset
    	 */
    	ctr = 0;
    	while (1) {
-			out_le16(&fpga->reflection_low,
-				REFLECTION_TESTPATTERN);
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-			if (in_le16(reflection_target) ==
-				REFLECTION_TESTPATTERN_INV)
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+			FPGA_GET_REG(k, reflection_low, &val);
+#else
+			FPGA_GET_REG(k, reflection_high, &val);
+#endif
+			if (val == REFLECTION_TESTPATTERN_INV)
    			break;
udelay(100000);
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 7d2899d..69faa69 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -67,6 +67,22 @@ enum {
    HWVER_110 = 1,
 };
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
+
 static inline void blank_string(int size)
 {
    int i;
@@ -100,10 +116,9 @@ int misc_init_r(void)
static void print_fpga_info(unsigned dev)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
    int fpga_state = get_fpga_state(dev);
unsigned unit_type;
@@ -111,6 +126,10 @@ static void print_fpga_info(unsigned dev)
    unsigned feature_channels;
    unsigned feature_expansion;
+	FPGA_GET_REG(dev, versions, &versions);
+	FPGA_GET_REG(dev, fpga_version, &fpga_version);
+	FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
    printf("FPGA%d: ", dev);
    if (fpga_state & FPGA_STATE_PLATFORM)
    	printf("(legacy) ");
@@ -242,8 +261,6 @@ int last_stage_init(void)
 {
    unsigned int k;
    unsigned int fpga;
-	struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
    int failed = 0;
    char str_phys[] = "Setup PHYs -";
    char str_serdes[] = "Start SERDES blocks";
@@ -281,17 +298,16 @@ int last_stage_init(void)
    /* take fpga serdes blocks out of reset */
    puts(str_serdes);
    udelay(500000);
-	out_le16(&fpga0->quad_serdes_reset, 0);
-	out_le16(&fpga1->quad_serdes_reset, 0);
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
+	FPGA_SET_REG(1, quad_serdes_reset, 0);
    blank_string(strlen(str_serdes));
/* take channels out of reset */
    puts(str_channels);
    udelay(500000);
    for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
    	for (k = 0; k < 32; ++k)
-			out_le16(ch0_config_int + 4 * k, 0);
+			FPGA_SET_REG(fpga, ch[k].config_int, 0);
    }
    blank_string(strlen(str_channels));
@@ -299,16 +315,16 @@ int last_stage_init(void)
    puts(str_locks);
    udelay(500000);
    for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
    	for (k = 0; k < 32; ++k) {
-			u16 status = in_le16(ch0_status_int + 4*k);
+			u16 status;
+			FPGA_GET_REG(k, ch[k].status_int, &status);
    		if (!(status & (1 << 4))) {
    			failed = 1;
    			printf("fpga %d channel %d: no serdes lock\n",
    				fpga, k);
    		}
    		/* reset events */
-			out_le16(ch0_status_int + 4*k, status);
+			FPGA_SET_REG(fpga, ch[k].status_int, 0);
    	}
    }
    blank_string(strlen(str_locks));
@@ -316,14 +332,14 @@ int last_stage_init(void)
    /* verify hicb_status */
    puts(str_hicb);
    for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
    	for (k = 0; k < 32; ++k) {
-			u16 status = in_le16(ch0_hicb_status_int + 4*k);
+			u16 status;
+			FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
    		if (status)
    			printf("fpga %d hicb %d: hicb status %04x\n",
    				fpga, k, status);
    		/* reset events */
-			out_le16(ch0_hicb_status_int + 4*k, status);
+			FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
    	}
    }
    blank_string(strlen(str_hicb));
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index a192c98..7429457 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -22,8 +22,8 @@
  */
#include <common.h>
-#include <i2c.h>
 #include <asm/io.h>
+#include <i2c.h>
#include <gdsys_fpga.h>
@@ -67,37 +67,46 @@ enum {
    CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
 };
+unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+
 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-	struct ihs_i2c *i2c = &fpga->i2c;
+	u16 val;
-	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
-		;
-	out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
-	out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+	do {
+		FPGA_GET_REG(screen, extended_interrupt, &val);
+	} while (val & (1 << 12));
+
+	FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
+	FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
 }
static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-	struct ihs_i2c *i2c = &fpga->i2c;
    unsigned int ctr = 0;
+	u16 val;
+
+	do {
+		FPGA_GET_REG(screen, extended_interrupt, &val);
+	} while (val & (1 << 12));
-	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
-		;
-	out_le16(&fpga->extended_interrupt, 1 << 14);
-	out_le16(&i2c->write_mailbox_ext, reg);
-	out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
-	while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+	FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
+	FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
+	FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
+
+	FPGA_GET_REG(screen, extended_interrupt, &val);
+	while (!(val & (1 << 14))) {
    	udelay(100000);
    	if (ctr++ > 5) {
    		printf("iic receive timeout\n");
    		break;
    	}
+		FPGA_GET_REG(screen, extended_interrupt, &val);
    }
-	return in_le16(&i2c->read_mailbox_ext) >> 8;
+
+	FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
+	return val >> 8;
 }
 #endif
@@ -129,7 +138,6 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
static void mpc92469ac_set(unsigned screen, unsigned int fout)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
    unsigned int n;
    unsigned int m;
    unsigned int bitval = 0;
@@ -150,7 +158,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
    	break;
    }
-	out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
+	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
 }
 #endif
@@ -265,14 +273,12 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
 static int osd_write_videomem(unsigned screen, unsigned offset,
    u16 *data, size_t charcount)
 {
-	struct ihs_fpga *fpga =
-		(struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
    unsigned int k;
for (k = 0; k < charcount; ++k) {
    	if (offset + k >= BUFSIZE)
    		return -1;
-		out_le16(&fpga->videomem + offset + k, data[k]);
+		FPGA_SET_REG(screen, videomem[offset + k], data[k]);
    }
return charcount;
@@ -282,7 +288,7 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
    unsigned screen;
-	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+	for (screen = 0; screen <= max_osd_screen; ++screen) {
    	unsigned x;
    	unsigned y;
    	unsigned charcount;
@@ -318,14 +324,15 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int osd_probe(unsigned screen)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-	struct ihs_osd *osd = &fpga->osd;
-	u16 version = in_le16(&osd->version);
-	u16 features = in_le16(&osd->features);
+	u16 version;
+	u16 features;
    unsigned width;
    unsigned height;
    u8 value;
+	FPGA_GET_REG(0, osd.version, &version);
+	FPGA_GET_REG(0, osd.features, &features);
+
    width = ((features & 0x3f00) >> 8) + 1;
    height = (features & 0x001f) + 1;
@@ -372,12 +379,15 @@ int osd_probe(unsigned screen)
    fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
 #endif
-	out_le16(&fpga->videocontrol, 0x0002);
-	out_le16(&osd->control, 0x0049);
+	FPGA_SET_REG(screen, videocontrol, 0x0002);
+	FPGA_SET_REG(screen, osd.control, 0x0049);
+
+	FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
+	FPGA_SET_REG(screen, osd.x_pos, 0x007f);
+	FPGA_SET_REG(screen, osd.y_pos, 0x005f);
-	out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
-	out_le16(&osd->x_pos, 0x007f);
-	out_le16(&osd->y_pos, 0x005f);
+	if (screen > max_osd_screen)
+		max_osd_screen = screen;
return 0;
 }
@@ -386,7 +396,7 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
    unsigned screen;
-	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+	for (screen = 0; screen <= max_osd_screen; ++screen) {
    	unsigned x;
    	unsigned y;
    	unsigned k;
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 5d6308f..f2832d1 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -139,6 +139,10 @@
#define CONFIG_SYS_FPGA_COUNT		2
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
 #define CONFIG_SYS_LATCH0_RESET		0xffff
 #define CONFIG_SYS_LATCH0_BOOT		0xffff
 #define CONFIG_SYS_LATCH1_RESET		0xffcf
diff --git a/include/configs/io.h b/include/configs/io.h
index 4950ad7..6693cba 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -246,6 +246,9 @@
#define CONFIG_SYS_FPGA_COUNT		1
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0xa2015480
diff --git a/include/configs/io64.h b/include/configs/io64.h
index bb29bed..7dbdfa6 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -514,6 +514,10 @@
#define CONFIG_SYS_FPGA_COUNT		2
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
 #define CONFIG_SYS_LATCH0_RESET		0xffff
 #define CONFIG_SYS_LATCH0_BOOT		0xffff
 #define CONFIG_SYS_LATCH1_RESET		0xffbf
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5972711..cf8ebba 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -252,6 +252,9 @@ int fpga_gpio_get(int pin);
#define CONFIG_SYS_FPGA_COUNT		1
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x02025080
diff --git a/include/configs/neo.h b/include/configs/neo.h
index be1c9ff..328b745 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -238,6 +238,9 @@
#define CONFIG_SYS_FPGA_COUNT		1
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
 /* Memory Bank 3 (Latches) initialization                      */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x92015480
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 1758d74..a53ab89 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -35,6 +35,23 @@ enum {
 int get_fpga_state(unsigned dev);
 void print_fpga_state(unsigned dev);
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+	fpga_set_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+	fpga_get_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
 struct ihs_gpio {
    u16 read;
    u16 clear;
@@ -83,6 +100,19 @@ struct ihs_fpga {
 #endif
#ifdef CONFIG_IO64
+
+struct ihs_fpga_channel {
+	u16 status_int;
+	u16 config_int;
+	u16 switch_connect_config;
+	u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+	u16 status_int;
+	u16 config_int;
+};
+
 struct ihs_fpga {
    u16 reflection_low;	/* 0x0000 */
    u16 versions;		/* 0x0002 */
@@ -91,12 +121,9 @@ struct ihs_fpga {
    u16 reserved_0[5];	/* 0x0008 */
    u16 quad_serdes_reset;	/* 0x0012 */
    u16 reserved_1[502];	/* 0x0014 */
-	u16 ch0_status_int;	/* 0x0400 */
-	u16 ch0_config_int;	/* 0x0402 */
-	u16 reserved_2[126];	/* 0x0404 */
-	u16 ch0_hicb_status_int;/* 0x0500 */
-	u16 ch0_hicb_config_int;/* 0x0502 */
-	u16 reserved_3[7549];	/* 0x0504 */
+	struct ihs_fpga_channel ch[32];		/* 0x0400 */
+	struct ihs_fpga_channel hicb_ch[32];	/* 0x0500 */
+	u16 reserved_2[7487];	/* 0x0580 */
    u16 reflection_high;	/* 0x3ffe */
 };
 #endif
@@ -116,7 +143,7 @@ struct ihs_fpga {
    u16 reflection_high;	/* 0x00fe */
    struct ihs_osd osd;	/* 0x0100 */
    u16 reserved_3[889];	/* 0x010e */
-	u16 videomem;		/* 0x0800 */
+	u16 videomem[31736];	/* 0x0800 */
 };
 #endif
@@ -137,7 +164,7 @@ struct ihs_fpga {
    u16 reserved_4[176];	/* 0x00a0 */
    struct ihs_osd osd;	/* 0x0200 */
    u16 reserved_5[761];	/* 0x020e */
-	u16 videomem;		/* 0x0800 */
+	u16 videomem[31736];	/* 0x0800 */
 };
 #endif
-- 
1.8.3


    

[U-Boot] [PATCH v3 1/6] powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

dirk.eibach＠gdsys.cc