Rune and Yuli,
thank you for your replies. I tried out Rune's hints and found the board resetting continously after initialization of the SDRAM. I enabled the debug messages in the SDRAM initialization sequence and found the following memory controller settings:
U-Boot 0.4.5 (Jul 28 2003 - 14:18:33)
MPC8260 Reset Status: External Soft, External Hard
MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 264000000, scc_clk 66000000, brg_clk 66000000 - cpu_clk 198000000, cpm_clk 132000000, bus_clk 66000000
CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 198 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: memctl->memc_mptpr = 0x00001900 memctl->memc_psrt = 0x00000021 memctl->memc_br2 = 0x00000041 memctl->memc_or2 = 0xff001080 memctl->memc_psdmr = 0xeb6eb493 ramaddr = 0x00000008 memctl->memc_psdmr = 0xcb6eb493 memctl->memc_psdmr = 0xdb6eb493 memctl->memc_psdmr = 0xc36eb493 SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB
In the u-boot-0.3.0 source tree I found that the memory controller was programmed with hard-set values. Trying these values I found that u-boot started to the prompt without problems. The settings are listed below:
U-Boot 0.4.5 (Jul 28 2003 - 16:44:07)
MPC8260 Reset Status: Software Watchdog, External Soft, External Hard
MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 264000000, scc_clk 66000000, brg_clk 66000000 - cpu_clk 198000000, cpm_clk 132000000, bus_clk 66000000
CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 198 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: memctl->memc_mptpr = 0x00001900 memctl->memc_psrt = 0x00000021 memctl->memc_br2 = 0x00000041 memctl->memc_or2 = 0xff001080 memctl->memc_psdmr = 0x296eb452 <=> 0xeb6eb493 ramaddr = 0x00000008 memctl->memc_psdmr = 0x096eb452 <=> 0xcb6eb493 memctl->memc_psdmr = 0x196eb452 <=> 0xdb6eb493 memctl->memc_psdmr = 0x416eb452 <=> 0xc36eb493 SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB FLASH: 8 MB *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: FCC2 ETHERNET Hit any key to stop autoboot =>
Playing with the parameters I found that the problem is located in the SDAM bits of the PSDMR register which have to be programmed for my board as shown in the second setting. Any ideas?
I have another question according the CIP and BMS settings of the HRCW. They are both set to '1' which means that exceptions are vectored to 0x000n_nnnn and boot memory region is located at 0x0000_0000. I tried out to set those bits to '0', it didn't work. Why?
Best regards,
Thomas Schäfer
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