Hi Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Friday, June 26, 2020 5:51 PM To: Sagar Kadam sagar.kadam@sifive.com; U-Boot Mailing List <u- boot@lists.denx.de> Cc: Rick Chen rick@andestech.com; Jagan Teki jagan@amarulasolutions.com; Pragnesh Patel pragnesh.patel@sifive.com; Anup Patel anup.patel@wdc.com; Simon Glass sjg@chromium.org; Ye Li ye.li@nxp.com; Peng Fan peng.fan@nxp.com; Sean Anderson seanga2@gmail.com Subject: Re: [PATCH v5 3/3] riscv: cpu: check and append L1 cache to cpu features
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Hi Sagar,
On Thu, Jun 25, 2020 at 7:11 PM Bin Meng bmeng.cn@gmail.com wrote:
On Thu, Jun 25, 2020 at 4:12 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core.
=> cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com
drivers/cpu/riscv_cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
Reviewed-by: Bin Meng bin.meng@windriver.com
Just noticed that you sent to the wrong U-Boot ML address. Please resend this series to the ML. Thanks!
Yeah Bin, thanks for pointing it out. I received Undelivered notification about it. It was a mistake on my part. I am sending the v6 now
Thanks & BR, Sagar
Regards, Bin