Hi All,
I am trying to run the uboot on the custom P4080 board I have made the couple of modifications needed for the uboot to start running on the custom board. After relocating to RAM from the board_init_f it get struck in 0x7ff30700 please help me to debug this issue
U-Boot 2011.12 (Mar 19 2012 - 05:10:41)
CPU0: P4080E, Version: 2.0, (0x82080020) Core: E500MC, Version: 2.0, (0x80230020) Clock Configuration: CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz, CPU4:1500 MHz, CPU5:1500 MHz, CPU6:1500 MHz, CPU7:1500 MHz, CCB:800 MHz, DDR:650 MHz (1300 MT/s data rate) (Asynchronous), LBC:100 MHz FMAN1: 600 MHz FMAN2: 600 MHz PME: 600 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: P4080DS, 36-bit Addressing Reset Configuration Word (RCW): 00000000: 105a0000 00000000 1e1e181e 0000cccc 00000010: 34422200 3c3c2000 0e800000 e0000000 00000020: 00000000 00000000 00000000 c0128002 00000030: 10000000 00000000 00000000 00000000 SERDES Reference Clocks: I2C: Requested speed:100000, i2c_clk:400000000 FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:78125 Tr <= 1130 ns FDR:0x33, div:4096, ga:0x7, gb:0x4, a:16, b:256, speed:97656 Tr <= 490 ns divider:4000, est_div:4096, DFSR:20 FDR:0x33, speed:97656 Requested speed:100000, i2c_clk:400000000 FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:78125 Tr <= 1130 ns FDR:0x33, div:4096, ga:0x7, gb:0x4, a:16, b:256, speed:97656 Tr <= 490 ns divider:4000, est_div:4096, DFSR:20 FDR:0x33, speed:97656 ready SPI: ready DRAM: Initializing....using SPD starting at step 1 (STEP_GET_SPD) DDR: DDR III rank density = 0x 80000000 DDR: DDR III rank density = 0x 80000000 Computing lowest common DIMM parameters for memctl=0 Detected RDIMM VL33B1K69F-K9S all DIMMs ECC capable Computing lowest common DIMM parameters for memctl=1 Detected RDIMM VL33B1K69F-K9S all DIMMs ECC capable Reloading memory controller configuration options for memctl=0 mclk_ps = 1538 ps Reloading memory controller configuration options for memctl=1 mclk_ps = 1538 ps FSL Memory ctrl cg register computation FSLDDR: cs[0]_bnds = 0x000001ff FSLDDR: cs[0]_config = 0xa0064302 FSLDDR: cs[0]_config_2 = 0x00000000 FSLDDR: cs[1]_config = 0x80004302 FSLDDR: cs[2]_bnds = 0x000001ff CS2 is disabled. FSLDDR: cs[3]_bnds = 0x000001ff CS3 is disabled. FSLDDR: timing_cfg_0 = 0x50110104 FSLDDR: timing_cfg_3 = 0x01061000 FSLDDR: timing_cfg_1 = 0x98910a45 FSLDDR: timing_cfg_2 = 0x0fb8a8d4 FSLDDR: ddr_cdr1 = 0x80000000 FSLDDR: ddr_sdram_cfg = 0xd7044000 FSLDDR: ddr_sdram_cfg_2 = 0x24401324 FSLDDR: ddr_sdram_mode = 0x02021a50 FSLDDR: ddr_sdram_mode_3 = 0x00021a50 FSLDDR: ddr_sdram_mode_5 = 0x02021a50 FSLDDR: ddr_sdram_mode_5 = 0x02021a50 FSLDDR: ddr_sdram_mode_2 = 0x04100000 FSLDDR: ddr_sdram_mode_4 = 0x04100000 FSLDDR: ddr_sdram_mode_6 = 0x04100000 FSLDDR: ddr_sdram_mode_8 = 0x04100000 FSLDDR: ddr_sdram_interval = 0x13ce0100 FSLDDR: clk_cntl = 0x02800000 FSLDDR: timing_cfg_4 = 0x00000001 FSLDDR: timing_cfg_5 = 0x03401400 FSLDDR: zq_cntl = 0x89080600 FSLDDR: wrlvl_cntl = 0x8675f60b FSLDDR: ddr_sdram_rcw_1 = 0x000a5a00 FSLDDR: ddr_sdram_rcw_2 = 0x00200000 FSLDDR: cs[0]_bnds = 0x000001ff FSLDDR: cs[0]_config = 0xa0064302 FSLDDR: cs[0]_config_2 = 0x00000000 FSLDDR: cs[1]_config = 0x80004302 FSLDDR: cs[2]_bnds = 0x000001ff CS2 is disabled. FSLDDR: cs[3]_bnds = 0x000001ff CS3 is disabled. FSLDDR: timing_cfg_0 = 0x50110104 FSLDDR: timing_cfg_3 = 0x01061000 FSLDDR: timing_cfg_1 = 0x98910a45 FSLDDR: timing_cfg_2 = 0x0fb8a8d4 FSLDDR: ddr_cdr1 = 0x80000000 FSLDDR: ddr_sdram_cfg = 0xd7044000 FSLDDR: ddr_sdram_cfg_2 = 0x24401324 FSLDDR: ddr_sdram_mode = 0x02021a50 FSLDDR: ddr_sdram_mode_3 = 0x00021a50 FSLDDR: ddr_sdram_mode_5 = 0x02021a50 FSLDDR: ddr_sdram_mode_5 = 0x02021a50 FSLDDR: ddr_sdram_mode_2 = 0x04100000 FSLDDR: ddr_sdram_mode_4 = 0x04100000 FSLDDR: ddr_sdram_mode_6 = 0x04100000 FSLDDR: ddr_sdram_mode_8 = 0x04100000 FSLDDR: ddr_sdram_interval = 0x13ce0100 FSLDDR: clk_cntl = 0x02800000 FSLDDR: timing_cfg_4 = 0x00000001 FSLDDR: timing_cfg_5 = 0x03401400 FSLDDR: zq_cntl = 0x89080600 FSLDDR: wrlvl_cntl = 0x8675f60b FSLDDR: ddr_sdram_rcw_1 = 0x000a5a00 FSLDDR: ddr_sdram_rcw_2 = 0x00200000 memctl interleaving Programming controller 0 Programming controller 1 total_memory = 8589934592 6 GiB left unmapped DDR: 8 GiB (DDR3, 64-bit, CL=9, ECC off) DDR Controller Interleaving Mode: cache line DDR Chip-Select Interleaving Mode: CS0+CS1 Testing 0x00000000 - 0x7fffffff Testing 0x80000000 - 0xffffffff Testing 0x100000000 - 0x17fffffff Testing 0x180000000 - 0x1ffffffff Remap DDR 6 GiB left unmapped
Top of RAM usable for U-Boot at: 80000000 Reserving 786k for U-Boot at: 7ff30000 Reserving 1032k for malloc() at: 7fe2e000 Reserving 72 Bytes for Board Info at: 7fe2dfb8 Reserving 136 Bytes for Global Data at: 7fe2df30 Stack Pointer at: 7fe2df18 New Stack Pointer is: 7fe2df18
Group "db": Debug Register Group -------------------------------- csrr0=0x00000000 devent=0x00000000 nspd=0x00000000 dc2=0x00000000 csrr1=0x00000000 esr=0x08000000 pvr=0x80230020 dc4=0x00000000 dac1=0x00000000 iac1=0x00000000 srr0=0x7ff30700 wt1=0x00000000 dac2=0x00000000 iac2=0x00000000 srr1=0x00021200 wmsk=0x00000000 dbcr0=0x80000000 l1csr0=0x00010001 svr=0x82080020 ovcr=0x00000000 dbcr1=0x00000000 l1csr1=0x00010001 pc=0x7ff30700 edbcr0=0xc0000000 dbcr2=0x00000000 l1csr2=0x00000020 msr=0x00021200 edbsr0=0x00000000 dbcr4=0x00000000 l2csr0=0x00000000 ccsrbar=0xf:fe000000 edbsr1=0x08000000 dbsr=0x20000000 l2csr1=0x00000000 nia=0x7ff30700 dbsrwr=0x00000000 npidr=0x00000000 prsr=0x84000000 ddam=Write-only nspc=0x00000000 dc1=0x00000000
Group "default": Default Register Group --------------------------------------- gpr0=0x7ff315b4 gpr9=0x7fe2df30 gpr18=0x00000000 gpr27=0x7fe2df30 gpr1=0x7fe2df18 gpr10=0x7ff30000 gpr19=0x00000000 gpr28=0x7ff30000 gpr2=0xfdd03f70 gpr11=0xfdd03f30 gpr20=0x40002004 gpr29=0x7fe30000 gpr3=0x7ff30000 gpr12=0x7ff9b300 gpr21=0xfdcfff20 gpr30=0x7ff9b9bc gpr4=0x7ff9b000 gpr13=0x00164360 gpr22=0x00001000 gpr31=0x7fe2dfb8 gpr5=0x7ff9b000 gpr14=0x0f5c0000 gpr23=0x00000000 pc=0x7ff30700 gpr6=0x00000040 gpr15=0x8ffb0000 gpr24=0x00000400 gpr7=0x7ff9affc gpr16=0x00000000 gpr25=0x00000000 gpr8=0xeffeaffc gpr17=0x00000000 gpr26=0x7fe2df18
Group "fp": Floating Point Register Group ----------------------------------------- fpr0=0xfff80000:00008000 fpr11=0x00000000:00000000 fpr22=0x00000000:00000000 fpr1=0x00000000:00000000 fpr12=0x00000000:00000000 fpr23=0x00000000:00000000 fpr2=0x00000000:00000000 fpr13=0x00000000:00000000 fpr24=0x00000000:00000000 fpr3=0x00000000:00000000 fpr14=0x00000000:00000000 fpr25=0x00000000:00000000 fpr4=0x00000000:00000000 fpr15=0x00000000:00000000 fpr26=0x00000000:00000000 fpr5=0x00000000:00000000 fpr16=0x00000000:00000000 fpr27=0x00000000:00000000 fpr6=0x00000000:00000000 fpr17=0x00000000:00000000 fpr28=0x00000000:00000000 fpr7=0x00000000:00000000 fpr18=0x00000000:00000000 fpr29=0x00000000:00000000 fpr8=0x00000000:00000000 fpr19=0x00000000:00000000 fpr30=0x00000000:00000000 fpr9=0x00000000:00000000 fpr20=0x00000000:00000000 fpr31=0x3fb99900:00000000 fpr10=0x00000000:00000000 fpr21=0x00000000:00000000
Group "int": Interrupt registers -------------------------------- csrr0=0x00000000 givor13=0x00000000 ivor7=0x00000800 ivor38=0x00000000 csrr1=0x00000000 givor14=0x00000000 ivor8=0x00000900 ivor39=0x00000000 dear=0x00000000 givpr=0x00000000 ivor9=0x00000000 ivor40=0x00000000 dsrr0=0x00000000 gsrr0=0x00000000 ivor10=0x00000a00 ivor41=0x00000000 dsrr1=0x00000000 gsrr1=0x00000000 ivor11=0x00000b00 ivpr=0x7ff30000 esr=0x08000000 ivor0=0x00000100 ivor12=0x00000c00 mcsr=0x00000000 gdear=0x00000000 ivor1=0x00000200 ivor13=0x00000d00 mcsrr0=0x00000000 gesr=0x00000000 ivor2=0x00000300 ivor14=0x00000e00 mcsrr1=0x00000000 givor2=0x00000000 ivor3=0x00000400 ivor15=0x00000f00 srr0=0x7ff30700 givor3=0x00000000 ivor4=0x00000500 ivor35=0x00000000 srr1=0x00021200 givor4=0x00000000 ivor5=0x00000600 ivor36=0x00000000 givor8=0x00000000 ivor6=0x00000700 ivor37=0x00000000
Group "special": Special Purpose Register Group ----------------------------------------------- fpscr=0x00000000 l2csr0=0x00000000 sprg3=0x00000000 atbl=0x6df7c67f l2csr1=0x00000000 sprg4=0x00000000 atbu=0x000000fa l2erraddr=0x00000000 sprg5=0x00000000 bucsr=0x00000001 l2errattr=0x00000000 sprg6=0x00000000 ctr=0x00000000 l2errctl=0x00000000 sprg7=0x00000000 dac1=0x00000000 l2errdet=0x00000000 sprg8=0x00000000 dac2=0x00000000 l2errdis=0x00000000 sprg9=0x00000000 dbcr0=0x80000000 l2erreaddr=0x00000000 svr=0x82080020 dbcr1=0x00000000 l2errinjctl=0x00000000 tbl=0x269bc267 dbcr2=0x00000000 l2errinjhi=0x00000000 tbu=0x00000000 dbcr4=0x00000000 l2errinjlo=0x00000000 tcr=0x00000000 dbsr=0x20000000 l2errinten=0x00000000 tlb0cfg=0x04110200 dbsrwr=0x00000000 lpidr=0x00000000 tlb1cfg=0x401bc040 dec=0x00000000 lr=0x7ff315b4 tsr=0x00000000 decar=Write-only mas0=0x10080000 usprg0=0x00000000 eplc=0x00000000 mas1=0xc0000a00 xer=0x20000000 epr=0x00000000 mas2=0x40000000 pmc0=0x00000000 epsc=0x00000000 mas3=0x40000015 pmc1=0x00000000 gepr=0x00000000 mas4=0x00000000 pmc2=0x00000000 gpir=0x00000000 mas5=0x00000000 pmc3=0x00000000 gsprg0=0x00000000 mas6=0x00000000 pmlca0=0x00000000 gsprg1=0x00000000 mas7=0x00000000 pmlca1=0x00000000 gsprg2=0x00000000 mas8=0x00000000 pmlca2=0x00000000 gsprg3=0x00000000 mcar=0x00000000 pmlca3=0x00000000 hid0=0x80000080 mcaru=0x00000000 pmlcb0=0x00800000 iac1=0x00000000 mmucfg=0x064809c4 pmlcb1=0x00800000 iac2=0x00000000 mmucsr0=0x00000000 pmlcb2=0x00800000 l1cfg0=0x00b83820 msrp=0x00000000 pmlcb3=0x00800000 l1cfg1=0x00b83820 nspc=0x00000000 pmgc0=0x00000000 l1csr0=0x00010001 nspd=0x00000000 pc=0x7ff30700 l1csr1=0x00010001 pid=0x00000000 cr=0x28000022 l1csr2=0x00000020 pir=0x00000000 msr=0x00021200 l2captdatahi=0x00000000 pvr=0x80230020 ccsrbar=0xf:fe000000 l2captdatalo=0x00000000 sprg0=0x00000000 epcr=0x00000000 l2captecc=0x00000000 sprg1=0x00000000 cdcsr0=0xc8000000 l2cfg0=0x3cb1c002 sprg2=0x00000000
Thanks in advance.