This board has not been converted to CONFIG_DM_PCI by the deadline. Remove it.
Cc: Heiko Schocher hs@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc83xx/Kconfig | 5 - board/ve8313/Kconfig | 9 -- board/ve8313/MAINTAINERS | 6 - board/ve8313/Makefile | 6 - board/ve8313/ve8313.c | 209 ------------------------- configs/ve8313_defconfig | 160 ------------------- include/configs/ve8313.h | 260 ------------------------------- 7 files changed, 655 deletions(-) delete mode 100644 board/ve8313/Kconfig delete mode 100644 board/ve8313/MAINTAINERS delete mode 100644 board/ve8313/Makefile delete mode 100644 board/ve8313/ve8313.c delete mode 100644 configs/ve8313_defconfig delete mode 100644 include/configs/ve8313.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 23f7a60a44c0..0d24574ecc4d 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -8,10 +8,6 @@ choice prompt "Target select" optional
-config TARGET_VE8313 - bool "Support ve8313" - select ARCH_MPC8313 - config TARGET_VME8349 bool "Support vme8349" select ARCH_MPC8349 @@ -304,7 +300,6 @@ source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" source "board/tqc/tqm834x/Kconfig" -source "board/ve8313/Kconfig" source "board/gdsys/mpc8308/Kconfig"
endmenu diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig deleted file mode 100644 index a63744b1546e..000000000000 --- a/board/ve8313/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_VE8313 - -config SYS_BOARD - default "ve8313" - -config SYS_CONFIG_NAME - default "ve8313" - -endif diff --git a/board/ve8313/MAINTAINERS b/board/ve8313/MAINTAINERS deleted file mode 100644 index e3ca3325fcea..000000000000 --- a/board/ve8313/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VE8313 BOARD -M: Heiko Schocher hs@denx.de -S: Maintained -F: board/ve8313/ -F: include/configs/ve8313.h -F: configs/ve8313_defconfig diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile deleted file mode 100644 index d656bd93ab1d..000000000000 --- a/board/ve8313/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := ve8313.o diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c deleted file mode 100644 index 78d401e955eb..000000000000 --- a/board/ve8313/ve8313.c +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * - * Author: Scott Wood scottwood@freescale.com - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <pci.h> -#include <mpc83xx.h> -#include <ns16550.h> -#include <nand.h> - -#include <asm/bitops.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void disable_addr_trans (void); -extern void enable_addr_trans (void); - -int checkboard(void) -{ - puts("Board: ve8313\n"); - return 0; -} - -static long fixed_sdram(void) -{ - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize_log2 = __ilog2(msize); - - out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); - out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - __udelay(50000); - -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & - CSBNDS_EA)); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - - /* Currently we use only one CS, so disable the other bank. */ - out_be32(&im->ddr.cs_config[1], 0); - - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); - - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); - - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - sync(); - - /* enable DDR controller */ - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - - /* now check the real size */ - disable_addr_trans (); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); - enable_addr_trans (); -#endif - - return msize; -} - -int dram_init(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &im->im_lbc; - u32 msize; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - out_be32(&lbc->lbcr, 0x00040000); - out_be32(&lbc->mrtpr, 0x20000000); - sync(); - - /* return total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} - -#define VE8313_WDT_EN 0x00020000 -#define VE8313_WDT_TRIG 0x00040000 - -int board_early_init_f (void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; - -#if defined(CONFIG_HW_WATCHDOG) - /* enable WDT */ - clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); -#else - /* disable WDT */ - setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); -#endif - /* set WDT pins as output */ - setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG); - - return 0; -} - -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; - unsigned long reg; - - reg = in_be32(&gpio->dat); - if (reg & VE8313_WDT_TRIG) - clrbits_be32(&gpio->dat, VE8313_WDT_TRIG); - else - setbits_be32(&gpio->dat, VE8313_WDT_TRIG); -} -#endif - - -#if defined(CONFIG_PCI) -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - setbits_be32(&clk->occr, 0xe0000000); - - /* - * Configure PCI Local Access Windows - */ - out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR); - out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); - out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB); - - mpc83xx_pci_init(1, reg); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig deleted file mode 100644 index ed98cd1936ac..000000000000 --- a/configs/ve8313_defconfig +++ /dev/null @@ -1,160 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=32000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_VE8313=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_25_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_LALE_TIMING_EARLIER=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="PCI_MEM" -CONFIG_BAT1_BASE=0x80000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="PCI_MMIO" -CONFIG_BAT2_BASE=0x90000000 -CONFIG_BAT2_LENGTH_256_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="INITRAM_FLASH" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_BAT7=y -CONFIG_BAT7_NAME="FPGA_SRAM_NAND" -CONFIG_BAT7_BASE=0x60000000 -CONFIG_BAT7_LENGTH_256_MBYTES=y -CONFIG_BAT7_ACCESS_RW=y -CONFIG_BAT7_ICACHE_GUARDED=y -CONFIG_BAT7_DCACHE_GUARDED=y -CONFIG_BAT7_USER_MODE_VALID=y -CONFIG_BAT7_SUPERVISOR_MODE_VALID=y -CONFIG_NAND_LBLAWBAR_PRELIM_1=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0x61000000 -CONFIG_LBLAW1_NAME="NAND" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_SCY_5=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="NAND" -CONFIG_BR1_OR1_BASE=0x61000000 -CONFIG_BR1_ERRORCHECKING_BOTH=y -CONFIG_BR1_MACHINE_FCM=y -CONFIG_OR1_BCTLD_NOT_ASSERTED=y -CONFIG_OR1_SCY_2=y -CONFIG_OR1_CHT_TWO_CLOCK=y -CONFIG_OR1_RST_ONE_CLOCK=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="NVRAM" -CONFIG_BR2_OR2_BASE=0x60000000 -CONFIG_OR2_AM_128_KBYTES=y -CONFIG_OR2_SCY_3=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_XACS_EXTENDED=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_OR2_EHTR_8_CYCLE=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="SRAM" -CONFIG_BR3_OR3_BASE=0x62000000 -CONFIG_BR3_PORTSIZE_16BIT=y -CONFIG_OR3_AM_32_MBYTES=y -CONFIG_OR3_SCY_15=y -CONFIG_OR3_CSNT_EARLIER=y -CONFIG_OR3_XACS_EXTENDED=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_OR3_EAD_EXTRA=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_LCRR_EADC_3=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE060000 -CONFIG_ENV_ADDR_REDUND=0xFE080000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h deleted file mode 100644 index 91249f2eb482..000000000000 --- a/include/configs/ve8313.h +++ /dev/null @@ -1,260 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -/* - * ve8313 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE 1 - -/* - * On-board devices - * - */ - -/* - * Device configurations - */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ - -/* - * Manually set up DDR parameters, as this board does not - * have the SPD connected to I2C. - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_AP \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ALL \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80840102 */ - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (3 << TIMING_CFG0_RRT_SHIFT) \ - | (2 << TIMING_CFG0_WWT_SHIFT) \ - | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x0e720802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (5 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x029028c7 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03202000 */ -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* 0x44400232 */ -#define CONFIG_SYS_DDR_MODE_2 0x8000C000 - -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /*0x02000000*/ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_NOMZ \ - | DDRCDR_NZ_NOMZ \ - | DDRCDR_M_ODR) - /* 0x73000002 */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * NAND settings - */ -#define CONFIG_SYS_NAND_BASE 0x61000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 - - - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM - - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#if defined(CONFIG_PCI) -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif - -/* - * TSEC - */ - -#define CONFIG_TSEC1 -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC1" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x01 -#define TSEC1_FLAGS 0 -#define TSEC1_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Environment - */ -/* Address and size of Redundant Environment Sector */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* System IO Config */ -#define CONFIG_SYS_SICRH (0x01000000 | \ - SICRH_ETSEC2_B | \ - SICRH_ETSEC2_C | \ - SICRH_ETSEC2_D | \ - SICRH_ETSEC2_E | \ - SICRH_ETSEC2_F | \ - SICRH_ETSEC2_G | \ - SICRH_TSOBI1 | \ - SICRH_TSOBI2) - /* 0x010fff03 */ -#define CONFIG_SYS_SICRL (SICRL_LBC | \ - SICRL_SPI_A | \ - SICRL_SPI_B | \ - SICRL_SPI_C | \ - SICRL_SPI_D | \ - SICRL_ETSEC2_A) - /* 0x33fc0003) */ - -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME "ve8313" -#define CONFIG_UBOOTPATH ve8313/u-boot.bin - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ - "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "u-boot_addr_r=100000\0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " +${filesize};" \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize};" \ - "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ - -#endif /* __CONFIG_H */