Thierry,
-----Original Message----- From: Thierry Reding [mailto:thierry.reding@gmail.com] Sent: Friday, September 20, 2013 5:41 AM To: Tom Warren Cc: u-boot@lists.denx.de Subject: [PATCH] Tegra114: Fix PLLX M, N, P init settings
From: Jimmy Zhang jimmzhang@nvidia.com
The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly.
Signed-off-by: Jimmy Zhang jimmzhang@nvidia.com Reviewed-by: Tom Warren twarren@nvidia.com Signed-off-by: Thierry Reding treding@nvidia.com
arch/arm/cpu/arm720t/tegra-common/cpu.c | 36 +++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..2c50034 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -50,7 +50,13 @@ int get_num_cpus(void) */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { /* T20: 1 GHz */
- /* n, m, p, cpcon */
- /*
* Field Bits Width* n 17:8 10* m 4:0 5* p 22:20 3*//* n, m, p, cpcon */@@ -58,6 +64,12 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { },
/* T25: 1.2 GHz */
- /*
* Field Bits Width* n 17:8 10* m 4:0 5* p 22:20 3*/@@ -65,17 +77,29 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { },
/* T30: 1.4 GHz */
- /*
* Field Bits Width* n 17:8 10* m 4:0 5* p 22:20 3*/
- /* T114: 1.4 GHz */
- {{ 862, 8, 0, 8},
{ 583, 8, 0, 4},{ 696, 12, 0, 8},{ 700, 13, 0, 8},
- /* T114: 1.9 GHz */
- /*
* Field Bits Width* n 15:8 8* m 7:0 8* p 23:20 4*/- {{ 108, 1, 1, 8}, /* actual: 702.0 MHz */
{ 73, 1, 1, 4}, /* actual: 700.8 MHz */{ 116, 1, 1, 8}, /* actual: 696.0 MHz */{ 108, 2, 1, 8}, /* actual: 702.0 MHz */};
-- 1.8.4
LGTM. Thanks for doing this. Acked-by: Tom Warren twarren@nvidia.com
-- nvpublic