-----Original Message----- From: Bin Meng [mailto:bmeng.cn@gmail.com] Sent: Monday, October 05, 2009 1:59 PM To: Dudhat Dipen-B09055 Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver
Hi Dipen,
On Thu, Oct 1, 2009 at 12:48 PM, Dudhat Dipen-B09055 Dipen.Dudhat@freescale.com wrote:
Hi Bin,
We can know the block transfer complete using IRQSTAT(Transfer Complete). But reading & writing in PIO mode takes time for byte by byte transfers and there is no way to poll that transfer, that's why I have added delay there.
Yes, I understand there is no such a register in Freescale eSDHC that provides status check for PIO mode. I am just wondering where the delay value 100 us comes from. Is it the required minimum value?
Dipen, Yes it's a minimum value. Less than that it hangs and read/write fails in PIO Mode.
I can add comment like, * Wait before last byte transfer complete *\ Is that ok ??
Sure, adding a comment line would help a lot.
Regards, Bin Meng
Thanks Dipen