Hi,
-----Ursprüngliche Nachricht----- Von: Jaehoon Chung [mailto:jh80.chung@samsung.com]
On 12/02/2016 10:24 PM, stefan.herbrechtsmeier@weidmueller.de wrote:
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.de
The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. Distinguish between base clock of the host controller and maximal supported peripheral clock frequency of the peripheral interface. This is needed for the zynq platform to support two sdhci ports with different IO routings.
I understood what your purpose is...When i checked your patch, i wonder one thing about dwmmc controller. There is also using dwmci_setup_cfg() and it is assigned to cfg-
f_min/max with max_clk/min_clk.
I think it also needs to take your approach, right?
The driver already use a different source clock (host->bus_hz / host->get_mmc_clk) for the calculation in its own set_ios / dwmmi_setup_bus function.
do you have any plan for dwmmc controller?
No, because it is only a local cosmetic rename and shouldn't be affected by my changes.
Regards Stefan
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