The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Siew Chin Lim elly.siew.chin.lim@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 9e8be282005..fb05c31d87b 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = "/soc/spi@ff705000"; - udc0 = &usb0; + udc0 = &usb1; }; };