From: Ye Li ye.li@nxp.com
iMX8MP has shifted market segment fuse one bit from 0x440 [7:6] to [6:5], correct it in imx common codes.
Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/cpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index a4d8f101b6..425d0f0327 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -385,6 +385,9 @@ u32 get_cpu_speed_grade_hz(void) */ #define OCOTP_TESTER3_TEMP_SHIFT 6
+/* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */ +#define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5 + u32 get_cpu_temp_grade(int *minc, int *maxc) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -394,7 +397,10 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) uint32_t val;
val = readl(&fuse->tester3); - val >>= OCOTP_TESTER3_TEMP_SHIFT; + if (is_imx8mp()) + val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT; + else + val >>= OCOTP_TESTER3_TEMP_SHIFT; val &= 0x3;
if (minc && maxc) {