Now that we don't use SRAM C for the SPL stack anymore, there is no need to clock down AHB1 to 100 MHz. Keeping it at the recommended 200 MHz allows faster peripherals.
This reverts commit 5bc88cc2be3a962005b6e5768e06ca8f6ffcb88d.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index be9fcfd..f7e93b0 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -230,12 +230,7 @@ struct sunxi_ccm_reg { #define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) #define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f)
-#if defined(CONFIG_MACH_SUN50I) -/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ -#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ -#else #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#endif
#define AXI_GATE_OFFSET_DRAM 0