Re: [PATCH v4 2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation

On Wed, Aug 09, 2023 at 09:11:32PM +0800, Shengyu Qu wrote:

Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues:

1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race)

Signed-off-by: Bo Gan ganboing@gmail.com Signed-off-by: Shengyu Qu wiagn233@outlook.com

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Changes since v2:

• Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)

Changes since v3:

• Revert v3's fix since original implementation is actually right

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arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ common/init/board_init.c | 3 +++ 3 files changed, 15 insertions(+), 25 deletions(-)

Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com