On Tue, 16 Jul 2019 at 01:20, Joe Hershberger joe.hershberger@ni.com wrote:
On Mon, Jul 15, 2019 at 4:57 PM Vladimir Oltean olteanv@gmail.com wrote:
Hi Joe,
On Mon, 15 Jul 2019 at 22:17, Joe Hershberger joe.hershberger@ni.com wrote:
On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean olteanv@gmail.com wrote:
From: Jianchao Wang jianchao.wang@nxp.com
The LS1021A-TSN is a development board built by VVDN/Argonboards in partnership with NXP.
It features the LS1021A SoC and the first-generation SJA1105T Ethernet switch for prototyping implementations of a subset of IEEE 802.1 TSN standards.
Supported boot media: microSD card (via SPL), QSPI flash.
Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which is 64 MB in size and has an erase sector size of 256KB (therefore, flashing the RCW would erase part of U-boot).
Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which is only 32 MB in size but has an erase sector size of 64KB (therefore the RCW image can be flashed without erasing U-boot).
To avoid the problems above, the U-boot base address has been selected at 0x100000 (the start of the 5th 256KB erase sector), which works for all board revisions. Actually 0x40000 would have been enough, but 0x100000 is common for all Layerscape devices.
eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is disabled.
Signed-off-by: Xiaoliang Yang xiaoliang.yang@nxp.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com Signed-off-by: Jianchao Wang jianchao.wang@nxp.com Signed-off-by: Changming Huang jerry.huang@nxp.com
[Vladimir] Code taken from https://github.com/openil/u-boot (which itself is mostly copied from ls1021a-iot) and adapted with the following changes:
- Add a008850 errata workaround
- Converted eTSEC, MMC to DM to avoid all build warnings
- Plugged in distro boot feature, including support for extlinux.conf
- Added defconfig for QSPI boot
- Added the board/freescale/ls1021atsn/README.rst for initial setup
Signed-off-by: Vladimir Oltean olteanv@gmail.com
[ ... ]
+int board_early_init_f(void) +{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;+#ifdef CONFIG_TSEC_ENET
/* Clear BD & FR bits for big endian BD's and frame data (aka setNit: Multi-line comment format. I'm curious why checkpatch.pl doesn't catch this sometimes.
What seems to be the problem with this? Do you prefer to see a first line with just " /* "?
Yes. See [1] and [2]. I tried to make the intent more clear at [2].
[1] - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Docu... [2] - http://www.denx.de/wiki/U-Boot/CodingStyle
Oh, I wasn't aware that the coding style for the Linux net-next mailing list is the exception rather than the rule. Thanks for letting me know.
* correct eTSEC endianness). This is crucial in ensuring that it does* not report Data Parity Errors in its RX/TX FIFOs when attempting to* send traffic.*/clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);/* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);+#endif
+#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();+#endif
arch_soc_init();+#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot()) {timer_init();dram_init();}+#endif
return 0;+}
+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{
void (*second_uboot)(void);/* Clear the BSS */memset(__bss_start, 0, __bss_end - __bss_start);get_clocks();+#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())fsl_dp_disable_console();+#endif
preloader_console_init();dram_init();/* Allow OCRAM access permission as R/W */+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();enable_layerscape_ns_access();+#endif
/** if it is woken up from deep sleep, then jump to second* stage uboot and continue executing without recopyingU-Boot
* it from SD since it has already been reserved in memory* in last boot.*/if (is_warm_boot()) {second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;second_uboot();}board_init_r(NULL, 0);+} +#endif
+int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();+#endif
ls102xa_smmu_stream_id_init();+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();+#endif
+#ifdef CONFIG_U_QE
u_qe_init();+#endif
return 0;+}
+#if defined(CONFIG_SPL_BUILD) +void spl_board_init(void) +{
ls102xa_smmu_stream_id_init();+} +#endif
+#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();+#endif
return 0;+} +#endif
+#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));+#endif
+#ifdef CONFIG_FSL_CAAM
return sec_init();+#endif +} +#endif
+#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();+#endif +} +#endif
+int ft_board_setup(void *blob, bd_t *bd) +{
ft_cpu_setup(blob, bd);+#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);+#endif
return 0;+} diff --git a/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/board/freescale/ls1021atsn/ls102xa_pbi.cfg new file mode 100644 index 000000000000..a8ba184c6684 --- /dev/null +++ b/board/freescale/ls1021atsn/ls102xa_pbi.cfg
What is this file? Is it built by something?
Yes, search for CONFIG_SYS_FSL_PBL_PBI in include/configs/ls1021atsn.h and in the main Makefile. So the boot ROM of the SoC searches for a 512-bit wide data structure starting with sector 8 of the MMC called RCW (Reset Configuration Word). This defines PLL frequencies, SerDes protocols, pinmuxing etc on the SoC. The RCW can also have a sequence of PBL (Pre-Boot Loader) commands appended to it - generally these are memory write operations that do stuff such as errata workarounds before the execution transfers to the boot loader. Actually I believe, but can't prove, that it is the PBL who copies the U-Boot SPL from MMC into an internal SRAM called OCRAM (on-chip RAM) before transferring the execution to it. I say I can't prove this because I would have expected to recognize this block copy command in the file you asked about. The takeaway is that for MMC-based booting, the RCW and PBI commands are packaged together in a file called u-boot-with-spl-pbl.bin. For QSPI-based booting that is not the case - the SPL and the OCRAM are not involved because the QSPI flash is memory-mapped so the CPU can execute the U-Boot image directly. In the case of booting from QSPI flash, the RCW and PBL commands are not packaged with the U-Boot image, but instead you're supposed to flash them separately. To be honest I don't know why it is like that - I'm not a big fan of keeping a relatively opaque hex dump of the RCW and PBL commands in U-Boot (let alone that the process is not the same for all boot sources).
Thanks for the explanation.
@@ -0,0 +1,15 @@ +#PBI commands
+09570200 ffffffff +09570158 00000300 +8940007c 21f47300
+# Configure Scratch register +09ee0200 10000000 +# Configure alternate space +09570158 00001000 +# Flush PBL data +096100c0 000FFFFF
+09ea085c 00502880 +09ea0560 80800000
[ ... ]
+/* SPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +/* QSPI */ +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +/* DSPI */ +#endif
+#ifdef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "ethernet@2d10000"
Where does this name come from? Is this not the first mac, i.e. would you get this without the explicit setting ethprime?
I don't know, I didn't try not setting this. It is the first MAC, yes.
I would recommend trying it without setting this. It's usually only helpful of you need the second as default or something.
+#endif
+/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif
+#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000
+#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256
+#define CONFIG_FSL_DEVICE_DISABLE
+#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \func(USB, usb, 0) \func(DHCP, dhcp, na)+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \"initrd_high=0xffffffff\0" \"fdt_high=0xffffffff\0" \"fdt_addr=0x64f00000\0" \"kernel_addr=0x61000000\0" \"kernelheader_addr=0x60800000\0" \"scriptaddr=0x80000000\0" \"scripthdraddr=0x80080000\0" \"fdtheader_addr_r=0x80100000\0" \"kernelheader_addr_r=0x80200000\0" \"kernel_addr_r=0x80008000\0" \"kernelheader_size=0x40000\0" \"fdt_addr_r=0x8f000000\0" \"ramdisk_addr_r=0xa0000000\0" \"load_addr=0x80008000\0" \"kernel_size=0x2800000\0" \"kernel_addr_sd=0x8000\0" \"kernel_size_sd=0x14000\0" \"kernelhdr_addr_sd=0x4000\0" \"kernelhdr_size_sd=0x10\0" \BOOTENV \"boot_scripts=ls1021atsn_boot.scr\0" \"boot_script_hdr=hdr_ls1021atsn_bs.out\0" \"scan_dev_for_boot_part=" \"part list ${devtype} ${devnum} devplist; " \"env exists devplist || setenv devplist 1; " \"for distro_bootpart in ${devplist}; do " \"if fstype ${devtype} " \"${devnum}:${distro_bootpart} " \"bootfstype; then " \"run scan_dev_for_boot; " \"fi; " \"done\0" \"scan_dev_for_boot=" \"echo Scanning ${devtype} " \"${devnum}:${distro_bootpart}...; " \"for prefix in ${boot_prefixes}; do " \"run scan_dev_for_scripts; " \"run scan_dev_for_extlinux; " \"done;" \"\0" \"boot_a_script=" \"load ${devtype} ${devnum}:${distro_bootpart} " \"${scriptaddr} ${prefix}${script}; " \"env exists secureboot && load ${devtype} " \"${devnum}:${distro_bootpart} " \"${scripthdraddr} ${prefix}${boot_script_hdr} " \"&& esbc_validate ${scripthdraddr};" \"source ${scriptaddr}\0" \"qspi_bootcmd=echo Trying load from qspi..;" \"sf probe && sf read $load_addr " \"$kernel_addr $kernel_size; env exists secureboot " \"&& sf read $kernelheader_addr_r $kernelheader_addr " \"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \"bootm $load_addr#$board\0" \"sd_bootcmd=echo Trying load from SD ..;" \"mmcinfo && mmc read $load_addr " \"$kernel_addr_sd $kernel_size_sd && " \"env exists secureboot && mmc read $kernelheader_addr_r " \"$kernelhdr_addr_sd $kernelhdr_size_sd " \" && esbc_validate ${kernelheader_addr_r};" \"bootm $load_addr#$board\0"+#undef CONFIG_BOOTCOMMAND +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt"+#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"+#endif
+/*
- Miscellaneous configurable options
- */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+#define CONFIG_LS102XA_STREAM_ID
+#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)+#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif
+#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+/*
- Environment
- */
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif
+#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_MISC_INIT_R
+#include <asm/fsl_secure_boot.h> +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
+#endif
2.17.1
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Thanks, -Vladimir _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Regards, -Vladimir