diff -urN u-boot_06JUN07/board/kb9202/Makefile u-boot_06JUN07_nand/board/kb9202/Makefile
--- u-boot_06JUN07/board/kb9202/Makefile	2007-06-06 12:46:44.000000000 -0700
+++ u-boot_06JUN07_nand/board/kb9202/Makefile	2007-06-06 17:33:55.000000000 -0700
@@ -28,7 +28,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= kb9202.o
+COBJS	:= kb9202.o nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff -urN u-boot_06JUN07/board/kb9202/nand.c u-boot_06JUN07_nand/board/kb9202/nand.c
--- u-boot_06JUN07/board/kb9202/nand.c	1969-12-31 17:00:00.000000000 -0700
+++ u-boot_06JUN07_nand/board/kb9202/nand.c	2007-06-06 18:06:34.000000000 -0700
@@ -0,0 +1,180 @@
+
+/*
+ * (C) Copyright 2006 KwikByte kb9200_dev@kwikbyte.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#include <asm-arm/arch-at91rm9200/hardware.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+
+/*
+ *	Board-specific function to access device control signals
+ *
+ * EN* on D28 (PB26 for ATL)
+ * ALE on A22
+ * CLE on A21
+ * RB* on D29 (PB27 for ATL)
+ */
+static void kb9202_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	switch(cmd) {
+		case NAND_CTL_SETCLE:
+			this->IO_ADDR_W += 0x200000;
+			break;
+		case NAND_CTL_CLRCLE:
+			this->IO_ADDR_W -= 0x200000;
+			break;
+		case NAND_CTL_SETALE:
+			this->IO_ADDR_W += 0x400000;
+			break;
+		case NAND_CTL_CLRALE:
+			this->IO_ADDR_W -= 0x400000;
+			break;
+		case NAND_CTL_SETNCE:
+#ifndef	CONFIG_KB9202B_ATL
+/*			AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC28; */
+			AT91C_BASE_PIOC->PIO_CODR = ((unsigned)1<<28);
+#else
+/*			AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB26; */
+			AT91C_BASE_PIOB->PIO_CODR = ((unsigned)1<<26);
+#endif
+			break;
+		case NAND_CTL_CLRNCE:
+#ifndef	CONFIG_KB9202B_ATL
+/*			AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC28; */
+			AT91C_BASE_PIOC->PIO_SODR = ((unsigned)1<<28);
+#else
+/*			AT91C_BASE_PIOB->PIO_SODR = AT91C_PIO_PB26; */
+			AT91C_BASE_PIOB->PIO_SODR = ((unsigned)1<<26);
+#endif
+			break;
+	}
+}
+
+
+/*
+ * Board-specific function to access the device ready signal.
+ */
+static int kb9202_nand_ready(struct mtd_info *mtd)
+{
+#ifndef	CONFIG_KB9202B_ATL
+/*	return (((AT91C_BASE_PIOC->PIO_PDSR) & AT91C_PIO_PC29) != 0); */
+	return (((AT91C_BASE_PIOC->PIO_PDSR) & ((unsigned)1<<29)) != 0);
+#else
+/*	return (((AT91C_BASE_PIOB->PIO_PDSR) & AT91C_PIO_PB27) != 0); */
+	return (((AT91C_BASE_PIOB->PIO_PDSR) & ((unsigned)1<<27)) != 0);
+#endif
+}
+
+
+/*
+ * Board-specific NAND init.  Copied from include/linux/mtd/nand.h for reference.
+ *
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @hwcontrol:		[BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ *			If set to NULL no access to ready/busy is available and the ready/busy information
+ *			is read from the chip status register
+ * @enable_hwecc:	[BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ *			be provided if a hardware ECC is available
+ * @eccmode:		[BOARDSPECIFIC] mode of ecc, see defines
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ *			special functionality. See the defines for further explanation
+*/
+/*
+ * This routine initializes controller and GPIOs.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	unsigned	value;
+
+	nand->hwcontrol = kb9202_hwcontrol;
+	nand->dev_ready = kb9202_nand_ready;
+/*	nand->enable_hwecc = NOT AVAILABLE */
+	nand->eccmode = NAND_ECC_SOFT;
+/*	nand->chip_delay = USE DEV READY */
+	nand->options &= ~(NAND_BUSWIDTH_16);
+
+	/* in case running outside of bootloader */
+	AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC);
+#ifdef	CONFIG_KB9202B_ATL
+	AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOB);
+#endif
+
+	/* setup nand flash access (allow ample margin) */
+	/* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
+	((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] =
+		AT91C_SMC2_WSEN |
+		(4 & AT91C_SMC2_NWS) |
+		((1 << 8) & AT91C_SMC2_TDF) |
+		AT91C_SMC2_DBW_8 |
+		((1 << 24) & AT91C_SMC2_RWSETUP) |
+		((1 << 29) & AT91C_SMC2_RWHOLD);
+
+	/* enable internal NAND controller */
+	value = *(AT91C_EBI_CSA);
+	value |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	*(AT91C_EBI_CSA) = value;
+
+	/* enable SMOE/SMWE */
+	AT91C_BASE_PIOC->PIO_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+	AT91C_BASE_PIOC->PIO_OER = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+
+	/* enable CE and BUSY\ signals */
+#ifndef	CONFIG_KB9202B_ATL
+/*
+	AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC28;
+	AT91C_BASE_PIOC->PIO_ODR = AT91C_PIO_PC29;
+	AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC28 | AT91C_PIO_PC29;
+	AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC28;
+*/
+	AT91C_BASE_PIOC->PIO_SODR = ((unsigned)1<<28);
+	AT91C_BASE_PIOC->PIO_ODR = ((unsigned)1<<29);
+	AT91C_BASE_PIOC->PIO_PER = ((unsigned)1<<28) | ((unsigned)1<<29);
+	AT91C_BASE_PIOC->PIO_OER = ((unsigned)1<<28);
+#else
+/*
+	AT91C_BASE_PIOB->PIO_SODR = AT91C_PIO_PB26;
+	AT91C_BASE_PIOB->PIO_ODR = AT91C_PIO_PB27;
+	AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB26 | AT91C_PIO_PB27;
+	AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB26;
+*/
+	AT91C_BASE_PIOB->PIO_SODR = ((unsigned)1<<26);
+	AT91C_BASE_PIOB->PIO_ODR = ((unsigned)1<<27);
+	AT91C_BASE_PIOB->PIO_PER = ((unsigned)1<<26) | ((unsigned)1<<27);
+	AT91C_BASE_PIOB->PIO_OER = ((unsigned)1<<26);
+#endif
+
+	return (0);
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff -urN u-boot_06JUN07/include/configs/kb9202.h u-boot_06JUN07_nand/include/configs/kb9202.h
--- u-boot_06JUN07/include/configs/kb9202.h	2007-06-06 12:54:51.000000000 -0700
+++ u-boot_06JUN07_nand/include/configs/kb9202.h	2007-06-06 17:46:07.000000000 -0700
@@ -43,6 +43,9 @@
 /* #define	CONFIG_KB9202		1	 KwikByte KB9202 board	*/
 #define CONFIG_KB9202B		1	/* KwikByte KB9202B board	*/
 
+/* Define the following to support special board variant 	*/
+/* #define	CONFIG_KB9202B_ATL */
+
 #define	CONFIG_KB920x		1	/* Any KB920x board		*/
 #undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define USE_920T_MMU		1
@@ -60,12 +63,24 @@
 #ifdef CONFIG_KB9202B
 #define	CONFIG_BOOTARGS	"console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
 #define	CONFIG_BOOTCOMMAND	"bootm 0x10000000"
+#define	NAND_MAX_CHIPS		1
+#define	CFG_MAX_NAND_DEVICE	1
+/*#define	CFG_NAND_BASE		AT91_SMARTMEDIA_BASE */
+#define	CFG_NAND_BASE		0x40000000
+#define	CONFIG_JFFS2_NAND
+#define	CONFIG_JFFS2_CMDLINE
+
+#define	MTDIDS_DEFAULT		"nand0=kb9202b-nand"
+#define	MTDPARTS_DEFAULT	"mtdparts=mtdparts=kb9202b-nand:-"
+
+/*#define	CONFIG_MTD_DEBUG */
+/*/#define	CONFIG_MTD_DEBUG_VERBOSE	MTD_DEBUG_LEVEL3 */
 #endif
 
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(128*1024)
+#define CFG_MALLOC_LEN		(1024*1024)
 #define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
@@ -86,12 +101,19 @@
 #define CONFIG_BOOTDELAY	1
 #define CONFIG_ENV_OVERWRITE	1
 
+#ifdef CONFIG_KB9202B
+#define	KB9202_REV_CMDS	CFG_CMD_NAND
+#else
+#define	KB9202_REV_CMDS	0
+#endif
+
 #define CONFIG_COMMANDS		\
 		       ((CONFIG_CMD_DFL | \
 		        CFG_CMD_I2C | \
 		        CFG_CMD_EEPROM | \
 			CFG_CMD_PING | \
 			CFG_CMD_DHCP | \
+			KB9202_REV_CMDS | \
 			CFG_CMD_JFFS2) & \
 		      ~(CFG_CMD_BDI | \
 			CFG_CMD_FPGA | \
@@ -122,7 +144,11 @@
 #define PHYS_FLASH_SIZE			0x200000
 #endif
 
+#ifdef	CONFIG_KB9202B_ATL
+#define CFG_MAX_FLASH_BANKS		0
+#else
 #define CFG_MAX_FLASH_BANKS		1
+#endif
 #define CFG_MAX_FLASH_SECT		256
 
 #define	CONFIG_HARD_I2C
