Add support for Qualcomm QRB4210-RB2 evaluation board (based on Qualcomm QRB4210 SoC).
Features: - Qualcomm Snapdragon QRB4210 (Robotics version of SM6115 SoC). - 2GiB RAM (on-board) [max: 8 GiB]. - 16GiB eMMC, uSD slot.
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to doc/board/qualcomm/qrb4210-rb2.rst.
Signed-off-by: Bhupesh Sharma bhupesh.sharma@linaro.org --- arch/arm/dts/Makefile | 1 + arch/arm/dts/qrb4210-rb2-uboot.dtsi | 24 ++++ arch/arm/dts/qrb4210-rb2.dtsi | 120 ++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 11 ++ arch/arm/mach-snapdragon/Makefile | 1 + .../include/mach/sysmap-qrb4210rb2.h | 46 +++++++ arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c | 35 +++++ board/qualcomm/qrb4210-rb2/Kconfig | 15 +++ board/qualcomm/qrb4210-rb2/MAINTAINERS | 6 + board/qualcomm/qrb4210-rb2/Makefile | 6 + board/qualcomm/qrb4210-rb2/qrb4210-rb2.c | 51 ++++++++ board/qualcomm/qrb4210-rb2/qrb4210-rb2.its | 64 ++++++++++ configs/qrb4210rb2_defconfig | 56 ++++++++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/qrb4210-rb2.rst | 79 ++++++++++++ include/configs/qrb4210-rb2.h | 21 +++ 16 files changed, 537 insertions(+) create mode 100644 arch/arm/dts/qrb4210-rb2-uboot.dtsi create mode 100644 arch/arm/dts/qrb4210-rb2.dtsi create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h create mode 100644 arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c create mode 100644 board/qualcomm/qrb4210-rb2/Kconfig create mode 100644 board/qualcomm/qrb4210-rb2/MAINTAINERS create mode 100644 board/qualcomm/qrb4210-rb2/Makefile create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.c create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.its create mode 100644 configs/qrb4210rb2_defconfig create mode 100644 doc/board/qualcomm/qrb4210-rb2.rst create mode 100644 include/configs/qrb4210-rb2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c160e884bf..b551c904d1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -534,6 +534,7 @@ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb +dtb-$(CONFIG_TARGET_QRB4210RB2) += qrb4210-rb2.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/dts/qrb4210-rb2-uboot.dtsi b/arch/arm/dts/qrb4210-rb2-uboot.dtsi new file mode 100644 index 0000000000..8588dc2bf6 --- /dev/null +++ b/arch/arm/dts/qrb4210-rb2-uboot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to handle QRB4210-RB2 pre-relocation devices + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ + +/ { + soc { + u-boot,dm-pre-reloc; + + pinctrl_west@500000 { + u-boot,dm-pre-reloc; + }; + + clock-controller@1400000 { + u-boot,dm-pre-reloc; + }; + + serial@4a90000 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/arm/dts/qrb4210-rb2.dtsi b/arch/arm/dts/qrb4210-rb2.dtsi new file mode 100644 index 0000000000..ba07263c4a --- /dev/null +++ b/arch/arm/dts/qrb4210-rb2.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QRB4210-RB2 evaluation board device tree source + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ + +/dts-v1/; + +#include "skeleton64.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/qcom,gcc-sm6115.h> + +/ { + model = "Qualcomm Technologies, Inc. QRB4210 RB2"; + compatible = "qcom,qrb4210-rb2", "qcom,qrb4210", "qcom,sm4250"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &debug_uart; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + tlmm: pinctrl_west@500000 { + compatible = "qcom,sm6115-pinctrl"; + reg = <0x00500000 0x400000>; + gpio-count = <114>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm_north 0 0 114>; + + /* DEBUG UART */ + debug_uart_on: debug_uart-default { + pins = "GPIO_12", "GPIO_13"; + function = "qup4"; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + debug_uart: serial@4a90000 { + compatible = "qcom,msm-geni-uart"; + reg = <0x04a90000 0x4000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&debug_uart_on>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000 0x04745000 0x1000>; + clock = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + bus-width = <8>; + + no-sdio; + non-removable; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + clock = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>; + bus-width = <4>; + + no-sdio; + }; + + spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c0a000 0x26000>, + <0x01c40000 0x1100>, + <0x03e00000 0x100000>; + reg-names = "cnfg", "core", "obsrvr"; + #address-cells = <1>; + #size-cells = <0>; + + pm6125: pm6125@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <1>; + #size-cells = <0>; + + pm6125_gpios: pm6125_gpios@c000 { + compatible = "qcom,pm6125-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-count = <9>; + #gpio-cells = <2>; + gpio-bank-name="pmic"; + }; + }; + }; + }; +}; + +#include "qrb4210-rb2-uboot.dtsi" diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 914f4d9605..f150192cbb 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -77,6 +77,16 @@ config TARGET_QCS404EVB - 1GiB RAM - 8GiB eMMC, uSD slot
+config TARGET_QRB4210RB2 + bool "Qualcomm Technologies, Inc. QRB4210 RB2" + select LINUX_KERNEL_IMAGE_HEADER + help + Support for Qualcomm Technologies, Inc. QRB4210 RB2 board. + Features: + - Qualcomm Snapdragon SM6115 / SM4250 SoC + - 2GiB RAM + - 16GiB eMMC + endchoice
source "board/qualcomm/dragonboard410c/Kconfig" @@ -84,5 +94,6 @@ source "board/qualcomm/dragonboard820c/Kconfig" source "board/qualcomm/dragonboard845c/Kconfig" source "board/samsung/starqltechn/Kconfig" source "board/qualcomm/qcs404-evb/Kconfig" +source "board/qualcomm/qrb4210-rb2/Kconfig"
endif diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 4ee6a3902e..eef584aaed 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -21,3 +21,4 @@ obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o obj-$(CONFIG_TARGET_QRB4210RB2) += clock-qrb4210-rb2.o +obj-$(CONFIG_TARGET_QRB4210RB2) += sysmap-qrb4210-rb2.o diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h new file mode 100644 index 0000000000..544e48cf00 --- /dev/null +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm SM6115 sysmap + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ +#ifndef _MACH_SYSMAP_SM6115_H +#define _MACH_SYSMAP_SM6115_H + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0) +#define APCS_GPLL_ENA_VOTE (0x79000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x79004) + +/* Root clock for QUPv3 WRAPPER0 */ +#define QUPV3_WRAPPER_0_BCR (0x1F000) + +/* Uart clock control registers */ +#define UART4_APPS_CBCR (0x1F604) +#define UART4_APPS_CMD_RCGR (0x1F608) +#define UART4_APPS_CFG_RCGR (0x1F60c) +#define UART4_APPS_M (0x1F610) +#define UART4_APPS_N (0x1F614) +#define UART4_APPS_D (0x1F618) + +/* SDCC1 controller clock control registers */ +#define SDCC1_BCR (0x38000) +#define SDCC1_APPS_CBCR (0x38004) +#define SDCC1_AHB_CBCR (0x38008) +#define SDCC1_CMD_RCGR (0x38028) +#define SDCC1_CFG_RCGR (0x3802c) +#define SDCC1_M (0x38030) +#define SDCC1_N (0x38034) +#define SDCC1_D (0x38038) + +/* SDCC2 controller clock control registers */ +#define SDCC2_BCR (0x1E000) +#define SDCC2_APPS_CBCR (0x1E004) +#define SDCC2_AHB_CBCR (0x1E008) +#define SDCC2_CMD_RCGR (0x1E00C) +#define SDCC2_CFG_RCGR (0x1E010) +#define SDCC2_M (0x1E014) +#define SDCC2_N (0x1E018) +#define SDCC2_D (0x1E01c) + +#endif diff --git a/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c b/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c new file mode 100644 index 0000000000..c08a6d7d9f --- /dev/null +++ b/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SM6115 memory map + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region sm6115_mem_map[] = { + /* Peripheral block */ + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + + /* Terminator */ + { 0 } +}; + +struct mm_region *mem_map = sm6115_mem_map; diff --git a/board/qualcomm/qrb4210-rb2/Kconfig b/board/qualcomm/qrb4210-rb2/Kconfig new file mode 100644 index 0000000000..485757e268 --- /dev/null +++ b/board/qualcomm/qrb4210-rb2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QRB4210RB2 + +config SYS_BOARD + default "qrb4210-rb2" + +config SYS_VENDOR + default "qualcomm" + +config SYS_SOC + default "sm6115" + +config SYS_CONFIG_NAME + default "qrb4210-rb2" + +endif diff --git a/board/qualcomm/qrb4210-rb2/MAINTAINERS b/board/qualcomm/qrb4210-rb2/MAINTAINERS new file mode 100644 index 0000000000..2b569bb983 --- /dev/null +++ b/board/qualcomm/qrb4210-rb2/MAINTAINERS @@ -0,0 +1,6 @@ +Qualcomm Technologies, Inc. QRB4210-RB2 evaluation board +M: Bhupesh Sharma bhupesh.sharma@linaro.org +S: Maintained +F: board/qualcomm/qrb4210-rb2/ +F: include/configs/qrb4210-rb2.h +F: configs/qrb4210rb2_defconfig diff --git a/board/qualcomm/qrb4210-rb2/Makefile b/board/qualcomm/qrb4210-rb2/Makefile new file mode 100644 index 0000000000..d3cebdd221 --- /dev/null +++ b/board/qualcomm/qrb4210-rb2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org +# + +obj-y += qrb4210-rb2.o diff --git a/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c new file mode 100644 index 0000000000..38c2c23f78 --- /dev/null +++ b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for QRB4210-RB2 + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ + +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <env.h> +#include <init.h> +#include <asm/cache.h> +#include <asm/gpio.h> +#include <asm/global_data.h> +#include <fdt_support.h> +#include <asm/psci.h> +#include <asm/arch/dram.h> + +#include <linux/arm-smccc.h> +#include <linux/psci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +static void show_psci_version(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + + printf("PSCI: v%ld.%ld\n", + PSCI_VERSION_MAJOR(res.a0), + PSCI_VERSION_MINOR(res.a0)); +} + +int board_init(void) +{ + show_psci_version(); + + return 0; +} + +void reset_cpu(void) +{ + psci_system_reset(); +} diff --git a/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its new file mode 100644 index 0000000000..df77874d60 --- /dev/null +++ b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its @@ -0,0 +1,64 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <1>; + + images { + kernel-1 { + description = "6.2-rc8"; + data = /incbin/("./qrb4210rb2_imgs/Image.gz"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0x80000000>; + entry = <0x80000000>; + hash-1 { + algo = "sha1"; + }; + }; + + ramdisk-1 { + description = "Initial ramdisk"; + data = /incbin/("./qrb4210rb2_imgs/initramfs-test-image-qemuarm64-20230209073803-1343.rootfs.cpio.gz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-1 { + description = "qrb4210-rb2-fdt"; + data = /incbin/("./qrb4210rb2_imgs/qrb4210-rb2.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x83000000>; + hash-1 { + algo = "sha1"; + }; + }; + + }; + + configurations { + default = "config-1"; + + config-1 { + description = "qrb4210-rb2 kernel-6.2-rc8 configuration"; + kernel = "kernel-1"; + ramdisk = "ramdisk-1"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/configs/qrb4210rb2_defconfig b/configs/qrb4210rb2_defconfig new file mode 100644 index 0000000000..d04e6af729 --- /dev/null +++ b/configs/qrb4210rb2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=19000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_DEFAULT_DEVICE_TREE="qrb4210-rb2" +CONFIG_TARGET_QRB4210RB2=y +CONFIG_IDENT_STRING="\nQualcomm QRB4210-RB2" +CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused" +CONFIG_SAVE_PREV_BL_FDT_ADDR=y +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_MISC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PHY_QCOM_USB_HS_28NM=y +CONFIG_PHY_QCOM_USB_SS=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_DM_RESET=y +CONFIG_MSM_GENI_SERIAL=y +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_MSM_GPIO=y +CONFIG_SPMI_MSM=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_LMB_MAX_REGIONS=64 diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index 0f9c429956..8b840a0d5a 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -9,3 +9,4 @@ Qualcomm dragonboard410c sdm845 qcs404 + qrb4210-rb2 diff --git a/doc/board/qualcomm/qrb4210-rb2.rst b/doc/board/qualcomm/qrb4210-rb2.rst new file mode 100644 index 0000000000..65815d2325 --- /dev/null +++ b/doc/board/qualcomm/qrb4210-rb2.rst @@ -0,0 +1,79 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bhupesh Sharma bhupesh.sharma@linaro.org + +QRB4210 RB2 +=========== + +About this +---------- +This document describes the information about Qualcomm QRB4210 RB2 board +and it's usage steps. + +U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader. +It is loaded as an Android boot image through ABL. + +Installation +------------ +Build +^^^^^ +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make qrb4210rb2_defconfig + $ make + +This will build ``u-boot.bin`` in the configured output directory. + +Generate FIT image +^^^^^^^^^^^^^^^^^^ +A ``qrb4210-rb2.its`` file can be found in ``board/qualcomm/qrb4210-rb2/`` directory. +It expects a folder as ``qrb4210rb2_imgs/`` in the main directory containing +pre-built kernel, dts and ramdisk images. See ``qrb4210-rb2.its`` for full path to +images. + +- Build FIT image:: + + mkimage -f qrb4210-rb2.its qrb4210-rb2.itb + +Pack android boot image +^^^^^^^^^^^^^^^^^^^^^^^ +We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel, +and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel +with appended dtb, so let's mimic linux to satisfy stock bootloader: + +- create dump dtb:: + + workdir=/tmp/prepare_payload + mkdir -p "$workdir" + cd "$workdir" + mock_dtb="$workdir"/payload_mock.dtb + + dtc -I dts -O dtb -o "$mock_dtb" << EOF + /dts-v1/; + / { + model = "Qualcomm Technologies, Inc. QRB4210 RB2"; + compatible = "qcom,qrb4210-rb2", "qcom,sm6115"; + + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + chosen { }; + }; + EOF + +- gzip u-boot ``gzip u-boot.bin`` +- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb`` + +Now we've got everything to build android boot image::: + + mkbootimg --kernel u-boot.bin.gz-dtb \ + --ramdisk qrb4210-rb2.itb --pagesize 4096 \ + --base 0x80000000 --output boot.img + +Flash image on qrb4210 rb2 using fastboot method. diff --git a/include/configs/qrb4210-rb2.h b/include/configs/qrb4210-rb2.h new file mode 100644 index 0000000000..80b9c5e2dd --- /dev/null +++ b/include/configs/qrb4210-rb2.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for QRB4210-RB2 board + * + * (C) Copyright 2023 Bhupesh Sharma bhupesh.sharma@linaro.org + */ + +#ifndef __CONFIGS_QRB4210RB2_H +#define __CONFIGS_QRB4210RB2_H + +#include <linux/sizes.h> +#include <asm/arch/sysmap-qrb4210rb2.h> + +#define CFG_SYS_BAUDRATE_TABLE { 115200 } + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x5000000\0" \ + "bootm_low=0x80000000\0" \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif