21 Sep
2014
21 Sep
'14
6:12 p.m.
On 3 September 2014 17:37, Simon Glass sjg@chromium.org wrote:
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm/master and now in mainline.