Re: [PATCH 1/2] riscv: andes_plicsw: Fix IPI during OpenSBI invocation

On Tue, Jul 04, 2023 at 07:13:20PM +0800, Yu Chien Peter Lin wrote:

On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI.

This patch also updates the information about PLICSW.

Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com

arch/riscv/lib/andes_plicsw.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-)

Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com