This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/freescale/mpc8568mds/Kconfig | 12 - board/freescale/mpc8568mds/MAINTAINERS | 6 - board/freescale/mpc8568mds/Makefile | 13 - board/freescale/mpc8568mds/bcsr.c | 61 ---- board/freescale/mpc8568mds/bcsr.h | 93 ------ board/freescale/mpc8568mds/ddr.c | 56 ---- board/freescale/mpc8568mds/law.c | 41 --- board/freescale/mpc8568mds/mpc8568mds.c | 356 ----------------------- board/freescale/mpc8568mds/tlb.c | 84 ------ configs/MPC8568MDS_defconfig | 3 - include/configs/MPC8568MDS.h | 490 -------------------------------- 12 files changed, 1219 deletions(-) delete mode 100644 board/freescale/mpc8568mds/Kconfig delete mode 100644 board/freescale/mpc8568mds/MAINTAINERS delete mode 100644 board/freescale/mpc8568mds/Makefile delete mode 100644 board/freescale/mpc8568mds/bcsr.c delete mode 100644 board/freescale/mpc8568mds/bcsr.h delete mode 100644 board/freescale/mpc8568mds/ddr.c delete mode 100644 board/freescale/mpc8568mds/law.c delete mode 100644 board/freescale/mpc8568mds/mpc8568mds.c delete mode 100644 board/freescale/mpc8568mds/tlb.c delete mode 100644 configs/MPC8568MDS_defconfig delete mode 100644 include/configs/MPC8568MDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9c58526..2e4edb3 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -43,9 +43,6 @@ config TARGET_P5040DS config TARGET_MPC8536DS bool "Support MPC8536DS"
-config TARGET_MPC8568MDS - bool "Support MPC8568MDS" - config TARGET_MPC8569MDS bool "Support MPC8569MDS"
@@ -136,7 +133,6 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig deleted file mode 100644 index 4e178c5..0000000 --- a/board/freescale/mpc8568mds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8568MDS - -config SYS_BOARD - default "mpc8568mds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8568MDS" - -endif diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS deleted file mode 100644 index 379d8cc..0000000 --- a/board/freescale/mpc8568mds/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8568MDS BOARD -#M: - -S: Maintained -F: board/freescale/mpc8568mds/ -F: include/configs/MPC8568MDS.h -F: configs/MPC8568MDS_defconfig diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile deleted file mode 100644 index 612fb51..0000000 --- a/board/freescale/mpc8568mds/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2004-2007 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8568mds.o -obj-y += bcsr.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c deleted file mode 100644 index 4a6105c..0000000 --- a/board/freescale/mpc8568mds/bcsr.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -#include "bcsr.h" - -void enable_8568mds_duart(void) -{ - volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); - volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ - *devices = 0; /* Enable all peripheral devices */ - bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ -} - -void enable_8568mds_flash_write(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[9] |= 0x01; -} - -void disable_8568mds_flash_write(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[9] &= ~(0x01); -} - -void enable_8568mds_qe_mdio(void) -{ - u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[7] |= 0x01; -} - -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) -void reset_8568mds_uccs(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - /* Turn off UCC1 & UCC2 */ - out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); - out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); - - /* Mode is RGMII, all bits clear */ - out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK | - BCSR_UCC2_MODE_MSK)); - - /* Turn UCC1 & UCC2 on */ - out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN); - out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); -} -#endif diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h deleted file mode 100644 index 215534e..0000000 --- a/board/freescale/mpc8568mds/bcsr.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include <common.h> - -/* BCSR Bit definitions - * BCSR 0 * - 0:3 ccb sys pll - 4:6 cfg core pll - 7 cfg boot seq - - * BCSR 1 * - 0:2 cfg rom lock - 3:5 cfg host agent - 6 PCI IO - 7 cfg RIO size - - * BCSR 2 * - 0:4 QE PLL - 5 QE clock - 6 cfg PCI arbiter - - * BCSR 3 * - 0 TSEC1 reduce - 1 TSEC2 reduce - 2:3 TSEC1 protocol - 4:5 TSEC2 protocol - 6 PHY1 slave - 7 PHY2 slave - - * BCSR 4 * - 4 clock enable - 5 boot EPROM - 6 GETH transactive reset - 7 BRD write potect - - * BCSR 5 * - 1:3 Leds 1-3 - 4 UPC1 enable - 5 UPC2 enable - 6 UPC2 pos - 7 RS232 enable - - * BCSR 6 * - 0 CFG ver 0 - 1 CFG ver 1 - 6 Register config led - 7 Power on reset - - * BCSR 7 * - 2 board host mode indication - 5 enable TSEC1 PHY - 6 enable TSEC2 PHY - - * BCSR 8 * - 0 UCC GETH1 enable - 1 UCC GMII enable - 3 UCC TBI enable - 5 UCC MII enable - 7 Real time clock reset - - * BCSR 9 * - 0 UCC2 GETH enable - 1 UCC2 GMII enable - 3 UCC2 TBI enable - 5 UCC2 MII enable - 6 Ready only - indicate flash ready after burning - 7 Flash write protect -*/ - -#define BCSR_UCC1_GETH_EN (0x1 << 7) -#define BCSR_UCC2_GETH_EN (0x1 << 7) -#define BCSR_UCC1_MODE_MSK (0x3 << 4) -#define BCSR_UCC2_MODE_MSK (0x3 << 0) - -/*BCSR Utils functions*/ - -void enable_8568mds_duart(void); -void enable_8568mds_flash_write(void); -void disable_8568mds_flash_write(void); -void enable_8568mds_qe_mdio(void); - -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) -void reset_8568mds_uccs(void); -#endif - -#endif /* __BCSR_H_ */ diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c deleted file mode 100644 index 6db92ef..0000000 --- a/board/freescale/mpc8568mds/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c deleted file mode 100644 index ae06966..0000000 --- a/board/freescale/mpc8568mds/law.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *5) 0xc000_0000 0xdfff_ffff SRIO 512MB - *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - */ - -struct law_entry law_table[] = { - /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c deleted file mode 100644 index a5c5d9d..0000000 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <spd_sdram.h> -#include <i2c.h> -#include <ioports.h> -#include <libfdt.h> -#include <fdt_support.h> - -#include "bcsr.h" - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GETH1 */ - {4, 10, 1, 0, 2}, /* TxD0 */ - {4, 9, 1, 0, 2}, /* TxD1 */ - {4, 8, 1, 0, 2}, /* TxD2 */ - {4, 7, 1, 0, 2}, /* TxD3 */ - {4, 23, 1, 0, 2}, /* TxD4 */ - {4, 22, 1, 0, 2}, /* TxD5 */ - {4, 21, 1, 0, 2}, /* TxD6 */ - {4, 20, 1, 0, 2}, /* TxD7 */ - {4, 15, 2, 0, 2}, /* RxD0 */ - {4, 14, 2, 0, 2}, /* RxD1 */ - {4, 13, 2, 0, 2}, /* RxD2 */ - {4, 12, 2, 0, 2}, /* RxD3 */ - {4, 29, 2, 0, 2}, /* RxD4 */ - {4, 28, 2, 0, 2}, /* RxD5 */ - {4, 27, 2, 0, 2}, /* RxD6 */ - {4, 26, 2, 0, 2}, /* RxD7 */ - {4, 11, 1, 0, 2}, /* TX_EN */ - {4, 24, 1, 0, 2}, /* TX_ER */ - {4, 16, 2, 0, 2}, /* RX_DV */ - {4, 30, 2, 0, 2}, /* RX_ER */ - {4, 17, 2, 0, 2}, /* RX_CLK */ - {4, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - - /* GETH2 */ - {5, 10, 1, 0, 2}, /* TxD0 */ - {5, 9, 1, 0, 2}, /* TxD1 */ - {5, 8, 1, 0, 2}, /* TxD2 */ - {5, 7, 1, 0, 2}, /* TxD3 */ - {5, 23, 1, 0, 2}, /* TxD4 */ - {5, 22, 1, 0, 2}, /* TxD5 */ - {5, 21, 1, 0, 2}, /* TxD6 */ - {5, 20, 1, 0, 2}, /* TxD7 */ - {5, 15, 2, 0, 2}, /* RxD0 */ - {5, 14, 2, 0, 2}, /* RxD1 */ - {5, 13, 2, 0, 2}, /* RxD2 */ - {5, 12, 2, 0, 2}, /* RxD3 */ - {5, 29, 2, 0, 2}, /* RxD4 */ - {5, 28, 2, 0, 2}, /* RxD5 */ - {5, 27, 2, 0, 3}, /* RxD6 */ - {5, 26, 2, 0, 2}, /* RxD7 */ - {5, 11, 1, 0, 2}, /* TX_EN */ - {5, 24, 1, 0, 2}, /* TX_ER */ - {5, 16, 2, 0, 2}, /* RX_DV */ - {5, 30, 2, 0, 2}, /* RX_ER */ - {5, 17, 2, 0, 2}, /* RX_CLK */ - {5, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - {4, 6, 3, 0, 2}, /* MDIO */ - {4, 5, 1, 0, 2}, /* MDC */ - - /* UART1 */ - {2, 0, 1, 0, 2}, /* UART_SOUT1 */ - {2, 1, 1, 0, 2}, /* UART_RTS1 */ - {2, 2, 2, 0, 2}, /* UART_CTS1 */ - {2, 3, 2, 0, 2}, /* UART_SIN1 */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -void local_bus_init(void); - -int board_early_init_f (void) -{ - /* - * Initialize local bus. - */ - local_bus_init (); - - enable_8568mds_duart(); - enable_8568mds_flash_write(); -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) - reset_8568mds_uccs(); -#endif -#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) - enable_8568mds_qe_mdio(); -#endif - -#ifdef CONFIG_SYS_I2C2_OFFSET - /* Enable I2C2_SCL and I2C2_SDA */ - volatile struct par_io *port_c; - port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); - port_c->cpdir2 |= 0x0f000000; - port_c->cppar2 &= ~0x0f000000; - port_c->cppar2 |= 0x0a000000; -#endif - - return 0; -} - -int checkboard (void) -{ - printf ("Board: 8568 MDS\n"); - - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - gur->lbiuiplldcr1 = 0x00078080; - if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; - } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; - } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; - } - - lbc->lcrr |= 0x00030000; - - asm("sync;isync;msync"); -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - asm("msync"); - - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * MPC8568 uses "new" 15-16 style addressing. - */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CONFIG_PCI) -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8568mds_config_table[] = { - { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -}; -#endif - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -/* - * pib_init() -- Initialize the PCA9555 IO expander on the PIB board - */ -void -pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC2/3 to PCI bus - */ - - /*switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0x00; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0x00; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf9; - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0x00; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - - asm("eieio"); - i2c_set_bus_num(orig_i2c_bus); -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int first_free_busno = 0; -#ifdef CONFIG_PCI1 - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - pci_speed = 66666000; - pci_32 = 1; - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - -#ifndef CONFIG_PCI_PNP - pci1_hose.config_table = pci_mpc8568mds_config_table; -#endif - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif - - fsl_pcie_init_board(first_free_busno); -} -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c deleted file mode 100644 index b5e2fec..0000000 --- a/board/freescale/mpc8568mds/tlb.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 Initializations */ - /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* - * TLBe 2: 1G Non-cacheable, guarded - * 0x80000000 512M PCI1 MEM - * 0xa0000000 512M PCIe MEM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1G, 1), - - /* - * TLBe 3: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCIe IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 4: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig deleted file mode 100644 index ac0ec8c..0000000 --- a/configs/MPC8568MDS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_MPC8568MDS=y diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h deleted file mode 100644 index 05e5a3d..0000000 --- a/include/configs/MPC8568MDS.h +++ /dev/null @@ -1,490 +0,0 @@ -/* - * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8568mds board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8568 1 /* MPC8568 specific */ -#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCI1 1 /* PCI controller */ -#define CONFIG_PCIE1 1 /* PCIE controller */ -#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_QE /* Enable QE */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif /*Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ -#define CONFIG_SYS_BCSR_BASE 0xf8000000 - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ - -/*Chip select 0 - Flash*/ -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 -#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 - -/*Chip slelect 1 - BCSR*/ -#define CONFIG_SYS_BR1_PRELIM 0xf8000801 -#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 - -/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - - -/* - * SDRAM on the LocalBus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - - -/*Chip select 2 - SDRAM*/ -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The bcsr registers are connected to CS3 on MDS. - * The new memory map places bcsr at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ -#define CONFIG_SYS_BCSR (0xf8000000) - -/*Chip slelect 4 - PIB*/ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 - -/*Chip select 5 - PIB*/ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 -#define CONFIG_SYS_OR5_PRELIM 0xffff69f7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser*/ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 - -/* - * General PCI - * Memory Addresses are mapped 1-1. I/O is mapped from 0 - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ - -#define CONFIG_SYS_PCIE1_NAME "Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ - -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -#ifdef CONFIG_QE -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "UEC0" -#endif -#define CONFIG_PHY_MODE_NEED_CHANGE -#define CONFIG_eTSEC_MDIO_BUS - -#ifdef CONFIG_eTSEC_MDIO_BUS -#define CONFIG_MIIM_ADDRESS 0xE0024520 -#endif - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif -#endif /* CONFIG_QE */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */