Hi Nikhil,
Thanks for the patch,
On 11/05/23 15:29, Nikhil M Jain wrote:
In spl_dcache_enable after setting up page table, set gd->relocaddr pointer with 64KB alignment, to get next location to reserve memory.
Signed-off-by: Nikhil M Jain n-jain1@ti.com
arch/arm/mach-k3/common.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 3c85caee57..a8bde942f2 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -614,6 +614,8 @@ void spl_enable_dcache(void) gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size);
- gd->relocaddr = gd->arch.tlb_addr;
- gd->relocaddr &= ~(0x10000 - 1);
I believe the 64Kb alignment requirement is for gd->arch.tlb_addr which was already set before. You may want to refer sequence given in arm_reserve_mmu
Regards Devarsh
dcache_enable(); #endif