From: Zhong Hongbo bocui107@gmail.com
Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V4: - None. Change for V3: - None. Change for V2: - Change the type of return for s3c64xx_get_base_sromc function. --- arch/arm/cpu/arm1176/s3c64xx/Makefile | 2 +- arch/arm/cpu/arm1176/s3c64xx/srom.c | 51 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 13 +++---- arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 +++++++++++++++++++++++++ board/samsung/smdk6400/smdk6400.c | 38 ++++++++++++++------ include/configs/smdk6400.h | 1 + 6 files changed, 134 insertions(+), 20 deletions(-) create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c create mode 100644 arch/arm/include/asm/arch-s3c64xx/sromc.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 2f37431..28786bf 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
-COBJS-$(CONFIG_S3C64XX) += speed.o +COBJS-$(CONFIG_S3C64XX) += speed.o srom.o COBJS-y += timer.o COBJS-$(CONFIG_PWM) += pwm.o
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c b/arch/arm/cpu/arm1176/s3c64xx/srom.c new file mode 100644 index 0000000..f1b2b34 --- /dev/null +++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 + * Zhong Hongbo bocui107n@gmail.com + * base on arch/arm/cpu/armv7/s5p-common/sromc.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sromc.h> +#include <asm/arch/s3c6400.h> +/* + * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM + * srom_bw_conf - SMC Band witdh reg configuration value + * srom_bc_conf - SMC Bank Control reg configuration value + */ +void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) +{ + u32 tmp; + struct s3c64xx_sromc *srom = + (struct s3c64xx_sromc *)s3c64xx_get_base_sromc(); + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= srom_bw_conf; + + writel(tmp, &srom->bw); + + /* Configure SMC_BC register */ + writel(srom_bc_conf, &srom->bc[srom_bank]); +} diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index b884763..d2ee9d2 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -471,14 +471,6 @@ */ #define ELFIN_SROM_BASE 0x70000000
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - /* * SDRAM Controller */ @@ -722,6 +714,11 @@ static inline unsigned long s3c64xx_get_base_timer(void) { return ELFIN_TIMER_BASE; } + +static inline unsigned long s3c64xx_get_base_sromc(void) +{ + return ELFIN_SROM_BASE; +} #endif
#endif /*__S3C6400_H__*/ diff --git a/arch/arm/include/asm/arch-s3c64xx/sromc.h b/arch/arm/include/asm/arch-s3c64xx/sromc.h new file mode 100644 index 0000000..fcad635 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/sromc.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2012 + * Zhong Hongbo bocui107@gmail.com + * + * base on arch/arm/include/asm/arch-s5pc1xx/sromc.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1 << ((x * 4) + 0)) +#define SROMC_BYTE_ADDR_MODE(x) (1 << ((x * 4) + 1)) +#define SROMC_WAIT_ENABLE(x) (1 << ((x * 4) + 2)) +#define SROMC_BYTE_ENABLE(x) (1 << ((x * 4) + 3)) + +#define SROMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s3c64xx_sromc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SROMC_H_ */ diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index c40d1f9..be0e18b 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -30,6 +30,7 @@
#include <common.h> #include <netdev.h> +#include <asm/arch/sromc.h> #include <asm/arch/s3c6400.h>
DECLARE_GLOBAL_DATA_PTR; @@ -53,25 +54,40 @@ static inline void delay(unsigned long loops) /* * Miscellaneous platform dependent initialisations */ - +#ifdef CONFIG_CS8900 static void cs8900_pre_init(void) { - SROM_BW_REG &= ~(0xf << 4); - SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); - SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) + - (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) + - (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC); + u32 smc_bw_conf, smc_bc_conf; + + /* Ethernet needs bus width of 16 bits */ + smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK) + | SROMC_WAIT_ENABLE(CONFIG_ENV_SROM_BANK) + | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK); + smc_bc_conf = SROMC_BC_TACS(CS8900_Tacs) + | SROMC_BC_TCOS(CS8900_Tcos) + | SROMC_BC_TACC(CS8900_Tacc) + | SROMC_BC_TCOH(CS8900_Tcoh) + | SROMC_BC_TAH(CS8900_Tah) + | SROMC_BC_TACP(CS8900_Tacp) + | SROMC_BC_PMC(CS8900_PMC); + + /* Select and configure the SROMC bank */ + s3c64xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + +} +#else +#define cs8900_pre_init() do {} while (0) +#endif + +static void norflash_srom_init(void) +{ + u32 smc_bw_conf, smc_bc_conf; }
int board_init(void) { cs8900_pre_init();
- /* NOR-flash in SROM0 */ - - /* Enable WAIT */ - SROM_BW_REG |= 4 | 8 | 1; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0; diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 6ea587d..b770463 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -78,6 +78,7 @@ /* * Hardware drivers */ +#define CONFIG_ENV_SROM_BANK 2 /* Select SROM Bank-2 for Ethernet*/ #define CONFIG_CS8900 /* we have a CS8900 on-board */ #define CONFIG_CS8900_BASE 0x18800300 #define CONFIG_CS8900_BUS16 /* follow the Linux driver */