Add a node to the device tree for Cr50. We want this to be on i2c port 2 so add 0 and 1 as well to make this work.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/dts/chromebook_coral.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 79b3e60db4..1e6e0e182f 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -28,6 +28,9 @@ cros-ec0 = &cros_ec; fsp = &fsp_s; spi0 = &spi; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; };
config { @@ -213,6 +216,28 @@ }; };
+ i2c_0: i2c2@16,0 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b010 0 0 0 0>; + }; + + i2c_1: i2c2@16,1 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b110 0 0 0 0>; + }; + + i2c_2: i2c2@16,2 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b210 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + tpm@50 { + reg = <0x50>; + compatible = "google,cr50"; + u-boot,i2c-offset-len = <0>; + }; + }; + serial: serial@18,2 { reg = <0x0200c210 0 0 0 0>; u-boot,dm-pre-reloc;