This patch also adds related code for spear3xx which is later used for spear310 and spear320 based boards
Signed-off-by: Vipin Kumar vipin.kumar@st.com
spear310evb: Add SPL support
Signed-off-by: Vipin Kumar vipin.kumar@st.com
spear320evb/spear320hmi: Add SPL support
Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/cpu/arm926ejs/spear/Makefile | 1 + arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c | 136 ++++++++++++++++++ arch/arm/include/asm/arch-spear/generic.h | 2 + arch/arm/include/asm/arch-spear/spear300.h | 23 ++++ arch/arm/include/asm/arch-spear/spear310.h | 22 +++ arch/arm/include/asm/arch-spear/spear320.h | 25 ++++ arch/arm/include/asm/arch-spear/spear3xx.h | 2 + board/st/spear/config.mk | 3 - board/st/spear/ddr/Makefile | 5 + board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c | 140 +++++++++++++++++++ .../spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c | 146 ++++++++++++++++++++ .../spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c | 146 ++++++++++++++++++++ .../spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c | 152 +++++++++++++++++++++ board/st/spear/spear300evb.c | 7 + board/st/spear/spear310evb.c | 31 +++++ board/st/spear/spear320hmi.c | 7 + board/st/spear/spear320plc.c | 7 + include/configs/spear.h | 4 + include/configs/spear300-evb.h | 5 + include/configs/spear310-evb.h | 5 + include/configs/spear3xx.h | 15 ++ 21 files changed, 881 insertions(+), 3 deletions(-) create mode 100644 board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 5ebdf65..fc2e136 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
ifdef CONFIG_SPL_BUILD COBJS-y += spl.o spl_boot.o spl_nand.o +COBJS-$(CONFIG_ARCH_SPEAR3XX) += spl-spear3xx.o COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c index 7e2bc98..972768d 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c +++ b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c @@ -22,6 +22,10 @@ */
#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/generic.h> +#include <asm/arch/misc.h>
int get_socrev(void) { @@ -33,3 +37,135 @@ int get_socrev(void) return SOC_SPEAR320; #endif } + +void spear3xx_ddr_comp_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddrpad; + u32 core3v3, ddr1v8; + + /* DDR pad register configurations */ + ddrpad = readl(&misc_p->ddr_pad); + ddrpad &= ~MISC_DDR_PAD_CNF_MSK; + ddrpad |= 0x3AA4; + writel(ddrpad, &misc_p->ddr_pad); + + /* Compensation register configurations */ + core3v3 = readl(&misc_p->core_3v3_compensation); + core3v3 &= 0x02fffff0; + core3v3 |= 0x78000008; + writel(core3v3, &misc_p->core_3v3_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x02fffff0; + ddr1v8 |= 0x78000008; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); +} + +/* getboottype() implementation for spear300 */ +#if defined(CONFIG_SOC_SPEAR300) +u32 getboottype(void) +{ + u32 bootmask = 0; + u32 bootstrap = (readl(CONFIG_SYS_TELECOM_BASE) >> SPEAR300_BOOTSHFT) & + SPEAR300_BOOTMASK; + + switch (bootstrap) { + case SPEAR300_USBBOOT: + bootmask |= BOOT_TYPE_USBD; + break; + case SPEAR300_TFTPI2CBOOT: + case SPEAR300_TFTPSPIBOOT: + bootmask |= BOOT_TYPE_TFTP; + break; + case SPEAR300_SNORBOOT: + bootmask |= BOOT_TYPE_SMI; + break; + case SPEAR300_PNOR8BOOT: + bootmask |= BOOT_TYPE_PNOR8; + break; + case SPEAR300_PNOR16BOOT: + bootmask |= BOOT_TYPE_PNOR16; + break; + case SPEAR300_NAND8BOOT: + case SPEAR300_NAND16BOOT: + bootmask |= BOOT_TYPE_NAND; + break; + case SPEAR300_UARTBOOT: + bootmask |= BOOT_TYPE_UART; + break; + default: + bootmask |= BOOT_TYPE_UNSUPPORTED; + break; + } + + return bootmask; +} +#elif defined(CONFIG_SOC_SPEAR310) +u32 getboottype(void) +{ + u32 bootmask = 0; + u32 bootstrap = (readl(SPEAR310_BOOT_REG) >> SPEAR310_BOOTSHFT) & + SPEAR310_BOOTMASK; + + switch (bootstrap) { + case SPEAR310_USBBOOT: + bootmask |= BOOT_TYPE_USBD; + break; + case SPEAR310_SNORBOOT: + bootmask |= BOOT_TYPE_SMI; + break; + case SPEAR310_PNORBOOT: + bootmask |= BOOT_TYPE_PNOR8 | BOOT_TYPE_PNOR16; + break; + case SPEAR310_NANDBOOT: + bootmask |= BOOT_TYPE_NAND; + break; + default: + bootmask |= BOOT_TYPE_UNSUPPORTED; + break; + } + + return bootmask; +} +#elif defined(CONFIG_SOC_SPEAR320) +u32 getboottype(void) +{ + u32 bootmask = 0; + u32 bootstrap = (readl(SPEAR320_BOOT_REG) >> SPEAR320_BOOTSHFT) & + SPEAR320_BOOTMASK; + + switch (bootstrap) { + case SPEAR320_USBBOOT: + bootmask |= BOOT_TYPE_USBD; + break; + case SPEAR320_TFTPI2CBOOT: + case SPEAR320_TFTPSPIBOOT: + bootmask |= BOOT_TYPE_TFTP; + break; + case SPEAR320_SNORBOOT: + bootmask |= BOOT_TYPE_SMI; + break; + case SPEAR320_PNOR8BOOT: + case SPEAR320_PNOR8NOACKBOOT: + bootmask |= BOOT_TYPE_PNOR8; + break; + case SPEAR320_PNOR16BOOT: + case SPEAR320_PNOR16NOACKBOOT: + bootmask |= BOOT_TYPE_PNOR16; + break; + case SPEAR320_NAND8BOOT: + case SPEAR320_NAND16BOOT: + bootmask |= BOOT_TYPE_NAND; + break; + case SPEAR320_UARTBOOT: + bootmask |= BOOT_TYPE_UART; + break; + default: + bootmask |= BOOT_TYPE_UNSUPPORTED; + break; + } + + return bootmask; +} +#endif diff --git a/arch/arm/include/asm/arch-spear/generic.h b/arch/arm/include/asm/arch-spear/generic.h index aa13b83..ffb8d4e 100644 --- a/arch/arm/include/asm/arch-spear/generic.h +++ b/arch/arm/include/asm/arch-spear/generic.h @@ -30,8 +30,10 @@ extern unsigned int setfreq_sz; extern void board_ddr_init(void); extern void board_lowlevel_late_init(void);
+/* Routines exported from SoC area */ extern void spear3xx_usbh_stop(void); extern void spear6xx_usbh_stop(void); +extern void spear3xx_ddr_comp_init(void);
extern u32 mpmc_conf_vals[];
diff --git a/arch/arm/include/asm/arch-spear/spear300.h b/arch/arm/include/asm/arch-spear/spear300.h index 4bfa619..66ed612 100644 --- a/arch/arm/include/asm/arch-spear/spear300.h +++ b/arch/arm/include/asm/arch-spear/spear300.h @@ -26,6 +26,19 @@
#include <asm/arch/spear3xx.h>
+#define CONFIG_SYS_TELECOM_BASE 0x50000000 + #define SPEAR300_BOOTSHFT 16 + #define SPEAR300_BOOTMASK 0xF + #define SPEAR300_USBBOOT 0x0 + #define SPEAR300_TFTPI2CBOOT 0x1 + #define SPEAR300_TFTPSPIBOOT 0x2 + #define SPEAR300_SNORBOOT 0x3 + #define SPEAR300_PNOR8BOOT 0x4 + #define SPEAR300_PNOR16BOOT 0x5 + #define SPEAR300_NAND8BOOT 0x6 + #define SPEAR300_NAND16BOOT 0x7 + #define SPEAR300_UARTBOOT 0xA + #define CONFIG_SYS_FSMC_BASE 0x94000000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) @@ -50,6 +63,16 @@ #define SPEAR300_MODE_CAMULCDW (0xE << 0) #define SPEAR300_MODE_CAM1LCD (0xF << 0)
+#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 1 +#define USBD_BOOT_SUPPORTED 1 +#define TFTP_BOOT_SUPPORTED 1 +#define UART_BOOT_SUPPORTED 1 +#define MMC_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 + #define SPEAR3XX_FUNC_ENB_REG SPEAR300_RAS_REG1
/* externs related to pinmux */ diff --git a/arch/arm/include/asm/arch-spear/spear310.h b/arch/arm/include/asm/arch-spear/spear310.h index 9d20237..91d0b53 100644 --- a/arch/arm/include/asm/arch-spear/spear310.h +++ b/arch/arm/include/asm/arch-spear/spear310.h @@ -38,12 +38,34 @@ #define CONFIG_SPEAR_RASBASE 0xB4000000
/* SPEAr310 RAS misc space registers and bitmasks */ +#define SPEAR310_BOOT_REG (CONFIG_SPEAR_RASBASE + 0x0) + #define SPEAR310_BOOTSHFT 0x0 + #define SPEAR310_BOOTMASK 0x7 + #define SPEAR310_USBBOOT 0x3 + #define SPEAR310_NANDBOOT 0x2 + #define SPEAR310_PNORBOOT 0x1 + #define SPEAR310_SNORBOOT 0x0 + #define SPEAR310_EMIBW_SHFT 0x3 + #define SPEAR310_EMIBW_MASK 0x18 + #define SPEAR310_EMIBW_8 0x0 + #define SPEAR310_EMIBW_16 0x1 + #define SPEAR310_EMIBW_32 0x2 #define SPEAR310_FUNCENB_REG (CONFIG_SPEAR_RASBASE + 0x8)
#define SPEAR310_SMII_REG (CONFIG_SPEAR_RASBASE + 0xC) #define SPEAR310_SMII_PHY_SHIFT 0x0 #define SPEAR310_SMII_PHY_MASK 0x3
+#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 1 +#define USBD_BOOT_SUPPORTED 1 +#define TFTP_BOOT_SUPPORTED 0 +#define UART_BOOT_SUPPORTED 0 +#define MMC_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 + #define SPEAR3XX_FUNC_ENB_REG SPEAR310_FUNCENB_REG
/* externs related to pinmux */ diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h index a027e10..5fe8fb0 100644 --- a/arch/arm/include/asm/arch-spear/spear320.h +++ b/arch/arm/include/asm/arch-spear/spear320.h @@ -44,6 +44,21 @@ #define SPEAR320_EXTENDED_MODE (1 << 4)
/* SPEAr320 RAS misc space registers and bitmasks */ +#define SPEAR320_BOOT_REG (CONFIG_SPEAR_RASBASE + 0x0) + #define SPEAR320_BOOTSHFT 0x0 + #define SPEAR320_BOOTMASK 0xF + #define SPEAR320_USBBOOT 0x0 + #define SPEAR320_TFTPI2CBOOT 0x1 + #define SPEAR320_TFTPSPIBOOT 0x2 + #define SPEAR320_SNORBOOT 0x3 + #define SPEAR320_PNOR8BOOT 0x4 + #define SPEAR320_PNOR16BOOT 0x5 + #define SPEAR320_NAND8BOOT 0x6 + #define SPEAR320_NAND16BOOT 0x7 + #define SPEAR320_UARTBOOT 0xA + #define SPEAR320_PNOR8NOACKBOOT 0xC + #define SPEAR320_PNOR16NOACKBOOT 0xD + #define SPEAR320_RASSELECT_REG (CONFIG_SPEAR_RASBASE + 0x000C)
#define SPEAR320_CONTROL_REG (CONFIG_SPEAR_RASBASE + 0x0010) @@ -452,6 +467,16 @@ #define PMX_SDHCI_CD_PORT_12_VAL 0 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
+#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 1 +#define USBD_BOOT_SUPPORTED 1 +#define TFTP_BOOT_SUPPORTED 1 +#define UART_BOOT_SUPPORTED 1 +#define MMC_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 + #define SPEAR3XX_FUNC_ENB_REG SPEAR320_RASSELECT_REG
/* externs related to pinmux */ diff --git a/arch/arm/include/asm/arch-spear/spear3xx.h b/arch/arm/include/asm/arch-spear/spear3xx.h index f0df4e6..f63c21e 100644 --- a/arch/arm/include/asm/arch-spear/spear3xx.h +++ b/arch/arm/include/asm/arch-spear/spear3xx.h @@ -33,6 +33,8 @@ #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000 #define CONFIG_SYS_SMI_BASE 0xFC000000 #define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SPEAR_MPMCREGS 109 + #define CONFIG_SPEAR_TIMERBASE 0xFC800000 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 #define CONFIG_SPEAR_MISCBASE 0xFCA80000 diff --git a/board/st/spear/config.mk b/board/st/spear/config.mk index 971d60a..49cc280 100644 --- a/board/st/spear/config.mk +++ b/board/st/spear/config.mk @@ -23,8 +23,5 @@
ifndef CONFIG_SPL_BUILD ALL-y += $(obj)u-boot.img - -ifdef CONFIG_MACH_SPEAR600EVB ALL-y += $(obj)spl/u-boot-spl.img endif -endif diff --git a/board/st/spear/ddr/Makefile b/board/st/spear/ddr/Makefile index 9f1c627..b1f975f 100644 --- a/board/st/spear/ddr/Makefile +++ b/board/st/spear/ddr/Makefile @@ -36,6 +36,11 @@ COBJS-$(CONFIG_DDR_MT47H64M16) += spear600_mt47h64m16_3_333_cl5_psync.o COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_333_cl5_psync.o COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_37e_166_cl4_sync.o COBJS-$(CONFIG_DDR_MT47H128M8) += spear600_mt47h128m8_3_266_cl5_async.o + +COBJS-$(CONFIG_DDR_MT46H32M16) += spr3xx_mt46h32m16_6_166_cl3.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_166_cl4_async.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_266_cl5_async.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_333_cl5_async.o endif
COBJS := $(sort $(COBJS-y)) diff --git a/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c b/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c new file mode 100644 index 0000000..ea2c466 --- /dev/null +++ b/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000001, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000001, + 0x02000001, + 0x04000201, + 0x02020102, + 0x03020202, + 0x02040202, + 0x00000002, + 0x00000000, + 0x01000403, + 0x02020002, + 0x01000203, + 0x0505053f, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x05060a00, + 0x0000023f, + 0x00030600, + 0x0a000000, + 0x00000a02, + 0x00001b1b, + 0x7f000000, + 0x001a0000, + 0x11030700, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00000000, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000000, + 0x00000000, + 0x0000050e, + 0x00000000, + 0x2d890000, + 0x00140014, + 0x00000000, + 0x00008236, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x003a0000, + 0x00010000, + 0x00200000, + 0x003c00f4, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010001, + 0x01010001, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000001 +}; +#endif diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c new file mode 100644 index 0000000..42457b3 --- /dev/null +++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, +#if defined(CONFIG_SPEAR_DUAL_DDR) + 0x01020003, + 0x01000102, + 0x04000202, +#else + 0x00000001, + 0x02000001, + 0x04000201, +#endif + 0x03030104, + 0x03020202, + 0x01040000, + 0x00000001, + 0x00000000, + 0x03000404, + 0x02020002, + 0x03000203, + 0x0505053f, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x07080a00, + 0x0000023f, + 0x00030600, + 0x09000000, + 0x00000a02, + 0x00001e1e, + 0x7F000000, + 0x005F0000, + 0x16030700, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00000000, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000000, + 0x00000000, + 0x0000050e, + 0x00000000, + 0x2d8900c8, + 0x00c80017, + 0x00000000, + 0x00008236, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x003a0000, + 0x00010000, + 0x00200000, + 0x003c00f4, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010001, + 0x01000000, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00430000, + 0x00000002 +}; +#endif diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c new file mode 100644 index 0000000..fc8524d --- /dev/null +++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_PLL2) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, +#if defined(CONFIG_SPEAR_DUAL_DDR) + 0x01020003, + 0x01000102, + 0x04000202, +#else + 0x00000001, + 0x02000001, + 0x04000201, +#endif + 0x03030104, + 0x03020202, + 0x01040000, + 0x00000001, + 0x00000000, + 0x03000405, + 0x02030002, + 0x04000204, + 0x0505053f, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0a0b0a00, + 0x0000023f, + 0x00040800, + 0x0e000000, + 0x00000f02, + 0x00002020, + 0x7f000000, + 0x005f0000, + 0x22040b00, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00000000, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000000, + 0x00000000, + 0x0000081b, + 0x00000000, + 0x48e100c8, + 0x00c80025, + 0x00000000, + 0x0000d056, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00230000, + 0x001f0023, + 0x00400000, + 0x00250099, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010001, + 0x01000000, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x006b0000, + 0x00000002 +}; +#endif diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c new file mode 100644 index 0000000..b8be8ae --- /dev/null +++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#if defined(CONFIG_ARCH_SPEAR3XX) && \ + (defined(CONFIG_SPEAR_DDR_PLL2) || defined(CONFIG_SPEAR_DDR_2HCLK)) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if defined(CONFIG_SPEAR_DDR_PLL2) + 0x00000001, + 0x00000000, +#else + 0x02020201, + 0x00000202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, +#if defined(CONFIG_SPEAR_DUAL_DDR) + 0x01020003, + 0x01000102, + 0x04000202, +#else + 0x00000001, + 0x02000001, + 0x04000201, +#endif + 0x03030104, + 0x03020202, + 0x01040000, + 0x00000001, + 0x00000000, + 0x03000405, + 0x03040002, + 0x04000305, + 0x0505053f, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0a0c0a00, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00001c1c, + 0x7c000000, + 0x005c0000, + 0x2b050e00, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00000000, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000000, + 0x00000000, + 0x00000a24, + 0x00000000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x001c0000, + 0x0019001c, + 0x00100000, + 0x001e007a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010001, + 0x01000000, + 0x00000001, + 0x00400000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00860000, + 0x00000002 +}; +#endif diff --git a/board/st/spear/spear300evb.c b/board/st/spear/spear300evb.c index 2ea598a..2f092fe 100644 --- a/board/st/spear/spear300evb.c +++ b/board/st/spear/spear300evb.c @@ -99,3 +99,10 @@ int board_eth_init(bd_t *bis) return ret; } #endif + +#if defined(CONFIG_SPL_BUILD) +void board_ddr_init(void) +{ + spear3xx_ddr_comp_init(); +} +#endif diff --git a/board/st/spear/spear310evb.c b/board/st/spear/spear310evb.c index 7f70008..fa5f5e2 100644 --- a/board/st/spear/spear310evb.c +++ b/board/st/spear/spear310evb.c @@ -32,6 +32,7 @@ #include <asm/arch/generic.h> #include <asm/arch/misc.h> #include <asm/arch/pinmux.h> +#include <asm/arch/spl_pnor.h>
#if defined(CONFIG_CMD_NAND) static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; @@ -109,3 +110,33 @@ int board_eth_init(bd_t *bis) return ret; } #endif + +#if defined(CONFIG_SPL_BUILD) +void board_ddr_init(void) +{ + spear3xx_ddr_comp_init(); +} + +/* +void soc_init(void) +{ + writel(0x2f7bc210, &misc_p->plgpio3_pad_prg); + writel(0x017bdef6, &misc_p->plgpio4_pad_prg); +} +*/ + +pnor_width_t get_pnor_width(void) +{ + u32 emi_buswidth = (readl(SPEAR310_BOOT_REG) & SPEAR310_EMIBW_MASK) >> + SPEAR310_EMIBW_SHFT; + + if (SPEAR310_EMIBW_8 == emi_buswidth) + return PNOR_WIDTH_8; + else if (SPEAR310_EMIBW_16 == emi_buswidth) + return PNOR_WIDTH_16; + else if (SPEAR310_EMIBW_32 == emi_buswidth) + return PNOR_WIDTH_32; + else + return PNOR_WIDTH_SEARCH; +} +#endif diff --git a/board/st/spear/spear320hmi.c b/board/st/spear/spear320hmi.c index 562bdda..886a79d 100644 --- a/board/st/spear/spear320hmi.c +++ b/board/st/spear/spear320hmi.c @@ -118,3 +118,10 @@ int board_mmc_init(bd_t *bis) return ret; } #endif + +#if defined(CONFIG_SPL_BUILD) +void board_ddr_init(void) +{ + spear3xx_ddr_comp_init(); +} +#endif diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c index 315fe2d..2a408df 100644 --- a/board/st/spear/spear320plc.c +++ b/board/st/spear/spear320plc.c @@ -135,3 +135,10 @@ int board_mmc_init(bd_t *bis) return ret; } #endif + +#if defined(CONFIG_SPL_BUILD) +void board_ddr_init(void) +{ + spear3xx_ddr_comp_init(); +} +#endif diff --git a/include/configs/spear.h b/include/configs/spear.h index 4cb551d..d960d47 100644 --- a/include/configs/spear.h +++ b/include/configs/spear.h @@ -199,6 +199,10 @@ #define CONFIG_SYS_DCACHE_OFF #endif
+#ifndef CONFIG_SYS_PNOR_BOOT_BASE + #define CONFIG_SYS_PNOR_BOOT_BASE 0x0 +#endif + #define CONFIG_OF_LIBFDT #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/spear300-evb.h b/include/configs/spear300-evb.h index e3f4ab4..2a222af 100644 --- a/include/configs/spear300-evb.h +++ b/include/configs/spear300-evb.h @@ -78,6 +78,11 @@ /* ST SMI (Serial flash) configurations */ #define CONFIG_ST_SMI
+/* SPL support */ +#define CONFIG_SPL +#define CONFIG_SPEAR_DDR_2HCLK +#define CONFIG_DDR_MT47H64M16 + #if defined(CONFIG_ENV_IS_IN_FLASH) /* Environment is in serial NOR flash */ #define CONFIG_ENV_ADDR 0xF8060000 diff --git a/include/configs/spear310-evb.h b/include/configs/spear310-evb.h index 505c8a4..12dd5eb 100644 --- a/include/configs/spear310-evb.h +++ b/include/configs/spear310-evb.h @@ -95,6 +95,11 @@ #define CONFIG_ST_SMI #endif
+/* SPL support */ +#define CONFIG_SPL +#define CONFIG_SPEAR_DDR_2HCLK +#define CONFIG_DDR_MT47H64M16 + /* CFI Driver configurations */ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_FLASH_CFI_DRIVER diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index e89e9c2..3f53b20 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -46,5 +46,20 @@ #define CONFIG_SYS_INIT_SP_ADDR (0xD2800000 + 0x2000 - \ GENERATED_GBL_DATA_SIZE)
+/* SPL configurations */ +#if defined(CONFIG_SPL) + #define CONFIG_SPL_TEXT_BASE 0xD2800B00 + #define CONFIG_SYS_SNOR_BOOT_BASE 0xF8010000 + #define CONFIG_SYS_NAND_BOOT_BLK 4 + + #define CONFIG_SPL_NO_CPU_SUPPORT_CODE + #define CONFIG_SPL_LIBCOMMON_SUPPORT + #define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_SPL_MTD_SUPPORT + #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" + #define CONFIG_SPL_LDSCRIPT \ + "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" +#endif + #include <configs/spear.h> #endif /* __CONFIG_SPEAR3XX_H */