[U-Boot] [PATCH v2 1/3] arm: dts: h6: sync with dts with Linux sunxi

12 Apr 2019

There are some differences between U-Boot and Linux device tree files.
Sync only the minor changes.
6ba2e45d57af - arm64: dts: allwinner: h6: move MMC pinctrl to dtsi <Clément Péron>
54eac67bbe3a - arm64: dts: allwinner: Fix pinctrl node names <Maxime Ripard>
31af04cd60d3 - arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string <Rob Herring>
Signed-off-by: Clément Péron peron.clem@gmail.com
---
 arch/arm/dts/sun50i-h6-orangepi.dtsi |  2 --
 arch/arm/dts/sun50i-h6-pine-h64.dts  |  4 ----
 arch/arm/dts/sun50i-h6.dtsi          | 16 ++++++++++------
 3 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi
index 0612c19cd9..3748dcaa70 100644
--- a/arch/arm/dts/sun50i-h6-orangepi.dtsi
+++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
@@ -24,8 +24,6 @@
 };
&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
    vmmc-supply = <&reg_cldo1>;
    cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
    bus-width = <4>;
diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts
index ceffc40810..a26314c084 100644
--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -42,16 +42,12 @@
 };
&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
    vmmc-supply = <&reg_cldo1>;
    cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
    status = "okay";
 };
&mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
    vmmc-supply = <&reg_cldo1>;
    vqmmc-supply = <&reg_bldo2>;
    non-removable;
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index cfa5fffcf6..5f01314703 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -19,28 +19,28 @@
    	#size-cells = <0>;
cpu0: cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
    		device_type = "cpu";
    		reg = <0>;
    		enable-method = "psci";
    	};
cpu1: cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
    		device_type = "cpu";
    		reg = <1>;
    		enable-method = "psci";
    	};
cpu2: cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
    		device_type = "cpu";
    		reg = <2>;
    		enable-method = "psci";
    	};
cpu3: cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
    		device_type = "cpu";
    		reg = <3>;
    		enable-method = "psci";
@@ -143,7 +143,7 @@
    			bias-pull-up;
    		};
-			uart0_ph_pins: uart0-ph {
+			uart0_ph_pins: uart0-ph-pins {
    			pins = "PH0", "PH1";
    			function = "uart0";
    		};
@@ -158,6 +158,8 @@
    		resets = <&ccu RST_BUS_MMC0>;
    		reset-names = "ahb";
    		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
    		status = "disabled";
    		#address-cells = <1>;
    		#size-cells = <0>;
@@ -186,6 +188,8 @@
    		resets = <&ccu RST_BUS_MMC2>;
    		reset-names = "ahb";
    		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
    		status = "disabled";
    		#address-cells = <1>;
    		#size-cells = <0>;
@@ -266,7 +270,7 @@
    		interrupt-controller;
    		#interrupt-cells = <3>;
-			r_i2c_pins: r-i2c {
+			r_i2c_pins: r-i2c-pins {
    			pins = "PL0", "PL1";
    			function = "s_i2c";
    		};
-- 
2.17.1


    