Faraday ftwdt010 watchdog is an architecture independant watchdog. It is usaually used in SoC chip design.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- drivers/watchdog/Makefile | 1 + drivers/watchdog/ftwdt010_wdt.c | 95 ++++++++++++++++++++++++++++++++++++++ drivers/watchdog/ftwdt010_wdt.h | 96 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/ftwdt010_wdt.c create mode 100644 drivers/watchdog/ftwdt010_wdt.h
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 6ab4d52..5579bf2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o +COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c new file mode 100644 index 0000000..8571f15 --- /dev/null +++ b/drivers/watchdog/ftwdt010_wdt.c @@ -0,0 +1,95 @@ +/* + * [origin: Linux kernel drivers/watchdog/ftwdt010_wdt.c] + * + * Watchdog driver for the FTWDT010 Watch Dog Driver + * + * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) + * Based on sa1100_wdt.c by Oleg Drokin green@crimea.edu + * Based on SoftDog driver by Alan Cox alan@redhat.com + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * 27/11/2004 Initial release, Faraday. + * 12/01/2011 Port to u-boot, Macpaul Lin. + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include "ftwdt010_wdt.h" + +/* + * Set the watchdog time interval. + * Counter is 32 bit. + */ +static int ftwdt010_wdt_settimeout(unsigned int timeout) +{ + unsigned int reg; + + struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE; + + debug("Activating WDT..\n"); + + /* Check if disabled */ + if (readl(&wd->wdcr) & ~FTWDT010_WDCR_ENABLE) { + printf("sorry, watchdog is disabled\n"); + return -1; + } + + /* + * In a 66MHz system, + * if you set WDLOAD as 0x03EF1480 (66000000) + * the reset timer is 1 second. + */ + reg = FTWDT010_WDLOAD(timeout * FTWDT010_TIMEOUT_FACTOR); + + writel(reg, &wd->wdload); + + return 0; +} + +void ftwdt010_wdt_reset() +{ + struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE; + + /* clear control register */ + writel(0, &wd->wdcr); + + /* Write Magic number */ + writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart); + + /* Enable WDT */ + writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr); +} + +void ftwdt010_wdt_disable() +{ + struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE; + + debug("Deactivating WDT..\n"); + + /* + * It was defined with CONFIG_WATCHDOG_NOWAYOUT in Linux + * + * Shut off the timer. + * Lock it in if it's a module and we defined ...NOWAYOUT + */ + writel(0, &wd->wdcr); +} + +void hw_watchdog_reset() +{ + ftwdt010_wdt_reset(); +} + +void hw_watchdog_init(void) +{ + /* set timer in ms */ + ftwdt010_wdt_settimeout(CONFIG_FTWDT010_HW_TIMEOUT * 1000); +} diff --git a/drivers/watchdog/ftwdt010_wdt.h b/drivers/watchdog/ftwdt010_wdt.h new file mode 100644 index 0000000..00daec5 --- /dev/null +++ b/drivers/watchdog/ftwdt010_wdt.h @@ -0,0 +1,96 @@ +/* + * [origin: Linux kernel drivers/watchdog/ftwdt010_wdt.c] + * + * Watchdog driver for the FTWDT010 Watch Dog Driver + * + * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) + * Based on sa1100_wdt.c by Oleg Drokin green@crimea.edu + * Based on SoftDog driver by Alan Cox alan@redhat.com + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * 27/11/2004 Initial release, Faraday. + * 12/01/2011 Port to u-boot, Macpaul Lin. + */ + +#ifndef __FTWDT010_H +#define __FTWDT010_H + +struct ftwdt010_wdt { + unsigned int wdcounter; /* Counter Reg - 0x00 */ + unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ + unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ + unsigned int wdcr; /* Control Reg - 0x0c */ + unsigned int wdstatus; /* Status Reg - 0x10 */ + unsigned int wdclear; /* Timer Clear - 0x14 */ + unsigned int wdintrlen; /* Interrupt Length - 0x18 */ +}; + +/* + * WDLOAD - Counter Auto Reload Register + * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. + * Which means in a 66MHz system, the period of Watch Dog timer reset is + * one second. + */ +#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) + +/* + * WDRESTART - Watch Dog Timer Counter Restart Register + * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will + * automatically reload WDLOAD to WDCOUNTER and restart counting. + */ +#define FTWDT010_WDRESTART_MAGIC 0x5AB9 + +/* WDCR - Watch Dog Timer Control Register */ +#define FTWDT010_WDCR_ENABLE (1 << 0) +#define FTWDT010_WDCR_RST (1 << 1) +#define FTWDT010_WDCR_INTR (1 << 2) +/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ +#define FTWDT010_WDCR_EXT (1 << 3) +/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. + * The clock source PCLK cannot be gated when system sleeps, even if + * WDCLOCK bit is turned on. + * + * Faraday’s Watch Dog timer can be driven by an external clock. The + * programmer just needs to write one to WdCR[WdClock] bit. + * + * Note: There is a limitation between EXTCLK and PCLK: + * EXTCLK cycle time / PCLK cycle time > 2. + * If the system does not need an external clock, + * just keep WdCR[WdClock] bit in its default value. + */ +#define FTWDT010_WDCR_CLOCK (1 << 4) + +/* + * WDSTATUS - Watch Dog Timer Status Register + * This bit is set when the counter reaches Zero + */ +#define FTWDT010_WDSTATUS(x) ((x) & 0x1) + +/* + * WDCLEAR - Watch Dog Timer Clear Register + * Writing one to this register will clear WDSTATUS. + */ +#define FTWDT010_WDCLEAR (1 << 0) + +/* + * WDINTRLEN - Watch Dog Timer Interrupt Length + * This register controls the duration length of wd_rst, wd_intr and wd_ext. + * The default value is 0xFF. + */ +#define FTWDT010_WDINTRLEN(x) ((x) & 0xff) + +/* + * Variable timeout should be set in ms. + * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. + * WDLOAD = timeout * TIMEOUT_FACTOR. + */ +#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ + +#endif /* __FTWDT010_H */