Liu Dave-R63238 <r63238 <at> freescale.com> writes:
For that reset address question, I think because p4080ds's FPGA can do
this address
decode and map 0xefffxxxx to 0xffffxxxx setting by SW7, is it right?
No. FPGA doesn't matter with it.
The e500mc core boot start address(0xFFFF_FFFC) will point to the end of CS0 Flash due to OR0[AM]=0. In this phase, the core is using the relative addressing. After you change the BR0,OR0, you can use absolute addressing.
Keep in mind, the bootloader is placed to the end of CS0, and the RCW is placed to the start of CS0.
I also has another quesition, if I choose boot from bank0, why RCW
should be
programmed into address 0xe8000000? is it a rule of chip design?
Thanks Dave,
It look same as other PQ2/3 which using BR0/OR0 to set boot vecror base address.
just confirm, do you know CPU will read RCW data before it jump to 0xFFFF_FFFC?
/Tony