From: Naga Sureshkumar Relli naga.sureshkumar.relli@xilinx.com
This patch adds ddrc memory controller node in dts. size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at fd090208 from this driver.
Signed-off-by: Naga Sureshkumar Relli nagasure@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 45209309c054..b68fb1a4a5fe 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -506,6 +506,13 @@ power-domains = <&pd_adma>; };
+ mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled";