From: Joy Zou joy.zou@nxp.com
Support NXP PMIC pf9453.
Reviewed-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Joy Zou joy.zou@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/power/pmic/Kconfig | 15 ++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pf9453.c | 173 ++++++++++++++++++++++++++++++++++++ include/power/pf9453.h | 71 +++++++++++++++ 4 files changed, 260 insertions(+) create mode 100644 drivers/power/pmic/pf9453.c create mode 100644 include/power/pf9453.h
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 420c4099937..42e405901de 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -171,6 +171,21 @@ config SPL_DM_PMIC_PCA9450 This config enables implementation of driver-model pmic uclass features for PMIC PCA9450 in SPL. The driver implements read/write operations.
+config DM_PMIC_PF9453 + bool "Enable Driver Model for PMIC PF9453" + depends on DM_I2C + help + This config enables implementation of driver-model pmic uclass features + for PMIC PF9453. The driver implements read/write operations. + +config SPL_DM_PMIC_PF9453 + bool "Enable Driver Model for PMIC PF9453 in SPL" + depends on SPL_DM_PMIC + depends on SPL_DM_I2C + help + This config enables implementation of driver-model pmic uclass features + for PMIC PF9453 in SPL. The driver implements read/write operations. + config DM_PMIC_PF0900 bool "Enable Driver Model for PMIC PF0900" depends on DM_I2C diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 74ace69daf5..7cee4ee0582 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o +obj-$(CONFIG_$(SPL_)DM_PMIC_PF9453) += pf9453.o obj-$(CONFIG_$(SPL_)DM_PMIC_PF0900) += pf0900.o obj-$(CONFIG_$(SPL_)DM_PMIC_PF5300) += pf5300.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o diff --git a/drivers/power/pmic/pf9453.c b/drivers/power/pmic/pf9453.c new file mode 100644 index 00000000000..893a7771d0e --- /dev/null +++ b/drivers/power/pmic/pf9453.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include <asm/global_data.h> +#include <asm-generic/gpio.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <i2c.h> +#include <linux/err.h> +#include <log.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/pf9453.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + /* buck */ + { .prefix = "b", .driver = PF9453_REGULATOR_DRIVER}, + { .prefix = "B", .driver = PF9453_REGULATOR_DRIVER}, + /* ldo */ + { .prefix = "l", .driver = PF9453_REGULATOR_DRIVER}, + { .prefix = "L", .driver = PF9453_REGULATOR_DRIVER}, + { }, +}; + +struct pf9453_priv { + struct gpio_desc *sd_vsel_gpio; +}; + +static int pf9453_reg_count(struct udevice *dev) +{ + return PF9453_REG_NUM; +} + +static bool is_reg_protect(uint reg) +{ + switch (reg) { + case PF9453_BUCK1OUT: + case PF9453_BUCK2OUT: + case PF9453_BUCK3OUT: + case PF9453_BUCK4OUT: + case PF9453_LDO1OUT_L: + case PF9453_LDO1OUT_H: + case PF9453_LDO2OUT: + case PF9453_LDOSNVS_CFG1: + case PF9453_BUCK2OUT_MAX_LIMIT: + case PF9453_BUCK2OUT_MIN_LIMIT: + return true; + default: + return false; + } +} + +static int pf9453_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + bool is_pro; + u32 val = PF9453_UNLOCK_KEY; + + is_pro = is_reg_protect(reg); + if (is_pro) { + if (dm_i2c_write(dev, PF9453_REG_LOCK, (uint8_t *)&val, 1)) { + pr_err("write error to device: %p register: %#x!\n", dev, reg); + return -EIO; + } + + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!\n", dev, reg); + return -EIO; + } + + val = PF9453_LOCK_KEY; + if (dm_i2c_write(dev, PF9453_REG_LOCK, (uint8_t *)&val, 1)) { + pr_err("write error to device: %p register: %#x!\n", dev, reg); + return -EIO; + } + } else { + + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!\n", dev, reg); + return -EIO; + } + } + + return 0; +} + +static int pf9453_read(struct udevice *dev, uint reg, uint8_t *buff, + int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("read error from device: %p register: %#x!\n", dev, reg); + return -EIO; + } + + return 0; +} + +static int pf9453_bind(struct udevice *dev) +{ + int children; + ofnode regulators_node; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, + pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static int pf9453_probe(struct udevice *dev) +{ + struct pf9453_priv *priv = dev_get_priv(dev); + unsigned int reset_ctrl; + int ret = 0; + + if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PF9453)) { + priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel", + GPIOD_IS_OUT | + GPIOD_IS_OUT_ACTIVE); + if (IS_ERR(priv->sd_vsel_gpio)) { + ret = PTR_ERR(priv->sd_vsel_gpio); + dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + if (ret) + return ret; + } + } + + if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + reset_ctrl = PF9453_PMIC_RESET_WDOG_B_CFG_WARM; + else + reset_ctrl = PF9453_PMIC_RESET_WDOG_B_CFG_COLD; + + return pmic_clrsetbits(dev, PF9453_RESET_CTRL, + PF9453_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl); +} + +static struct dm_pmic_ops pf9453_ops = { + .reg_count = pf9453_reg_count, + .read = pf9453_read, + .write = pf9453_write, +}; + +static const struct udevice_id pf9453_ids[] = { + { .compatible = "nxp,pf9453", .data = NXP_CHIP_TYPE_PF9453, }, + { } +}; + +U_BOOT_DRIVER(pmic_pf9453) = { + .name = "pf9453 pmic", + .id = UCLASS_PMIC, + .of_match = pf9453_ids, + .bind = pf9453_bind, + .probe = pf9453_probe, + .ops = &pf9453_ops, + .priv_auto = sizeof(struct pf9453_priv), +}; diff --git a/include/power/pf9453.h b/include/power/pf9453.h new file mode 100644 index 00000000000..fd9617edc2c --- /dev/null +++ b/include/power/pf9453.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef PF9453_H_ +#define PF9453_H_ + +#define PF9453_REGULATOR_DRIVER "pf9453_regulator" + +enum { + PF9453_REG_DEV_ID = 0x00, + PF9453_OTP_VER = 0x01, + PF9453_INT1 = 0x02, + PF9453_INT1_MSK = 0x03, + PF9453_INT1_STATUS = 0x04, + PF9453_VRFLT1_INT = 0x05, + PF9453_VRFLT1_MASK = 0x06, + PF9453_PWRON_STAT = 0x07, + PF9453_RESET_CTRL = 0x08, + PF9453_SW_RST = 0x09, + PF9453_PWR_CTRL = 0x0a, + PF9453_CONFIG1 = 0x0b, + PF9453_CONFIG2 = 0x0c, + PF9453_32K_CONFIG = 0x0d, + PF9453_BUCK1CTRL = 0x10, + PF9453_BUCK1OUT = 0x11, + PF9453_BUCK2CTRL = 0x14, + PF9453_BUCK2OUT = 0x15, + PF9453_BUCK2OUT_STBY = 0x1D, + PF9453_BUCK2OUT_MAX_LIMIT = 0x1F, + PF9453_BUCK2OUT_MIN_LIMIT = 0x20, + PF9453_BUCK3CTRL = 0x21, + PF9453_BUCK3OUT = 0x22, + PF9453_BUCK4CTRL = 0x2e, + PF9453_BUCK4OUT = 0x2f, + PF9453_LDO1OUT_L = 0x36, + PF9453_LDO1CFG = 0x37, + PF9453_LDO1OUT_H = 0x38, + PF9453_LDOSNVS_CFG1 = 0x39, + PF9453_LDOSNVS_CFG2 = 0x3a, + PF9453_LDO2CFG = 0x3b, + PF9453_LDO2OUT = 0x3c, + PF9453_BUCK_POK = 0x3d, + PF9453_LSW_CTRL1 = 0x40, + PF9453_LSW_CTRL2 = 0x41, + PF9453_REG_LOCK = 0x4e, + PF9453_REG_NUM, +}; + +int power_pf9453_init(unsigned char bus, unsigned char addr); + +enum { + NXP_CHIP_TYPE_PF9453 = 0, + NXP_CHIP_TYPE_AMOUNT +}; + +#define PF9453_UNLOCK_KEY 0x5c +#define PF9453_LOCK_KEY 0x0 + +#define PF9453_EN_MODE_MASK 0x3 +#define PF9453_BUCK_RUN_MASK 0x7f +#define PF9453_LDO1_MASK 0x7f +#define PF9453_LDO2_MASK 0x3f +#define PF9453_LDOSNVS_MASK 0x7f + +#define PF9453_PMIC_RESET_WDOG_B_CFG_MASK 0xc0 +#define PF9453_PMIC_RESET_WDOG_B_CFG_WARM 0x40 +#define PF9453_PMIC_RESET_WDOG_B_CFG_COLD 0x80 + +#endif