There are difference between upstream DT and the old DT in terms of reg base, reset gpio and syscon. Make the driver compatible with upstream DT.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- drivers/pci/pcie_starfive_jh7110.c | 59 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 569fbfd35c..51aca7359f 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -25,13 +25,19 @@ #include "pcie_plda_common.h"
/* system control */ -#define STG_SYSCON_K_RP_NEP_MASK BIT(8) +#define STG_SYSCON_PCIE0_BASE 0x48 +#define STG_SYSCON_PCIE1_BASE 0x1f8 + +#define STG_SYSCON_AR_OFFSET 0x78 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 +#define STG_SYSCON_AW_OFFSET 0x7c #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) #define STG_SYSCON_CLKREQ_MASK BIT(22) #define STG_SYSCON_CKREF_SRC_SHIFT 18 #define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) +#define STG_SYSCON_RP_NEP_OFFSET 0xe8 +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
DECLARE_GLOBAL_DATA_PTR;
@@ -41,9 +47,7 @@ struct starfive_pcie { struct reset_ctl_bulk rsts; struct gpio_desc reset_gpio; struct regmap *regmap; - u32 stg_arfun; - u32 stg_awfun; - u32 stg_rp_nep; + unsigned int stg_pcie_base; };
static int starfive_pcie_atr_init(struct starfive_pcie *priv) @@ -92,7 +96,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) struct starfive_pcie *priv = dev_get_priv(dev); struct udevice *syscon; struct ofnode_phandle_args syscfg_phandle; - u32 cells[4]; int ret;
/* get corresponding syscon phandle */ @@ -117,20 +120,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) return -ENODEV; }
- /* get syscon register offset */ - ret = dev_read_u32_array(dev, "starfive,stg-syscon", - cells, ARRAY_SIZE(cells)); - if (ret) { - dev_err(dev, "Get syscon register err %d\n", ret); - return -EINVAL; - } - - dev_dbg(dev, "Get syscon values: %x, %x, %x\n", - cells[1], cells[2], cells[3]); - priv->stg_arfun = cells[1]; - priv->stg_awfun = cells[2]; - priv->stg_rp_nep = cells[3]; - return 0; }
@@ -138,8 +127,9 @@ static int starfive_pcie_parse_dt(struct udevice *dev) { struct starfive_pcie *priv = dev_get_priv(dev); int ret; + u32 domain_nr;
- priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg"); + priv->plda.reg_base = (void *)dev_read_addr_name(dev, "apb"); if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required reg address range\n"); return -EINVAL; @@ -147,7 +137,7 @@ static int starfive_pcie_parse_dt(struct udevice *dev)
priv->plda.cfg_base = (void *)dev_read_addr_size_name(dev, - "config", + "cfg", &priv->plda.cfg_size); if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required config address range"); @@ -172,7 +162,18 @@ static int starfive_pcie_parse_dt(struct udevice *dev) return ret; }
- ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + ret = dev_read_u32(dev, "linux,pci-domain", &domain_nr); + if (ret) { + dev_err(dev, "Can't get pci domain: %d\n", ret); + return ret; + } + + if (domain_nr == 0) + priv->stg_pcie_base = STG_SYSCON_PCIE0_BASE; + else + priv->stg_pcie_base = STG_SYSCON_PCIE1_BASE; + + ret = gpio_request_by_name(dev, "perst-gpios", 0, &priv->reset_gpio, GPIOD_IS_OUT); if (ret) { dev_err(dev, "Can't get reset-gpio: %d\n", ret); @@ -208,12 +209,12 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, (i << PLDA_PHY_FUNC_SHIFT) << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, i << PLDA_PHY_FUNC_SHIFT);
@@ -222,11 +223,11 @@ static int starfive_pcie_init_port(struct udevice *dev)
/* Disable physical functions */ regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, 0); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, 0);
@@ -273,17 +274,17 @@ static int starfive_pcie_probe(struct udevice *dev) return ret;
regmap_update_bits(priv->regmap, - priv->stg_rp_nep, + priv->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, STG_SYSCON_K_RP_NEP_MASK, STG_SYSCON_K_RP_NEP_MASK);
regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CKREF_SRC_MASK, 2 << STG_SYSCON_CKREF_SRC_SHIFT);
regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CLKREQ_MASK, STG_SYSCON_CLKREQ_MASK);